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AR# 24756

9.1i ISE - Project Navigator does not allow .tb, .vhd, or .v files to be added to a project in place of .tbw, .xco, or .xaw sources


Keywords: VHDL, Verilog, test bench, waveform, core, IP, CORE Generator, generator, clocking wizard, DCM

A Xilinx-specific source such as a .tbw, .xco, or .xaw can be added to an ISE project. From Project Navigator, these sources can be selected, viewed, and re-customized in their respective GUI tools (Waveform Editor, CORE Generator, Clocking Wizard). At some point, you might want to replace the Xilinx-specific source with the HDL file(s) generated from them. To do this, you can remove the .tbw, .xco, or .xaw file and then add the generated .tb, .v, or .vhd file to the project. However, in ISE 9.1i, when attempting to add the HDL generated file, Project Navigator reports the following error:

"<file_name>.v(hd) is already in the project, it cannot be added again"


This issue occurs when a Xilinx-specific source is added to a project, and the generated HDL source files are added in the background for tracking in synthesis/implementation and simulation. In ISE 9.1i, these generated HDL files are not properly removed from the project when the Xilinx-specific source is removed.

This problem has been fixed in the latest 9.1i Service Pack available at:
The first service pack containing the fix is 9.1i Service Pack 2.
AR# 24756
Date 04/17/2009
Status Archive
Type General Article