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AR# 2478

M1 QuickHDL - How do I compile the HDL SimPrim, LogiBLOX, UniSim, and CORE Generator libraries (VHDL and Verilog)?


Keywords: qvhcom, qvlcom, QuickHDL, simulation, SimPrim, LogiBLOX, UniSim, VHDL, Verilog, VITAL

Urgency: Standard

General Description:
To perform timing or post-synthesis functional HDL simulation in M1, the Verilog and/or VHDL (VITAL) SimPrim models must be compiled for use in QuickHDL. If instantiated LogiBLOX and/or Unified library components are to be behaviorally simulated, the LogiBLOX and/or UniSim libraries must be compiled, as well.



M1 includes the following scripts that automatically compile the Verilog and VHDL simulation models for your particular version of QuickHDL:


For more information on using these scripts, see the accompanying README files. These scripts should be run by your system administrator.

NOTE: The Verilog compile script will only compile XC3000, XC4000X (not XC4000E), and XC5200 UniSim models (M1.4 and later only). To compile the UniSim libraries for other device families, see Part 2 of this Answer Record.


The information below is intended primarily for reference. As compile scripts for QuickHDL are included with the Mentor Graphics interface, you should not need the following instructions unless you wish to compile UniSim libraries for families not listed in the Verilog compile script (e.g., XC4000E or XC9500), have problems with the compile scripts, or need to perform a partial library compilation.

M1 contains three types of HDL simulation libraries, and CORE Generator contains one:

SimPrim - Library of generic simulation primitives
LogiBLOX - Library of LogiBLOX simulation models
UniSim - Library of Unified component simulation models (A1.4+)
XUL - COREGen VHDL Library containing some arithmetic functions

The instructions that follow refer to the following variables:

VERILOG_DESTN - Location for compiled Verilog libraries
Recommended setting: $XILINX/mentor/data/verilog

VHDL_DESTN - Location for compiled VHDL libraries
Recommended setting: $XILINX/mentor/data/vhdl

If you want logical library names to be available for all designs, set your QUICKHDL environment variable to the location of your master quickhdl.ini file:

For example:
setenv QUICKHDL $MGC_HOME/lib/quickhdl.ini

If QUICKHDL is not set when qhmap is run, the logical library mapping is done locally; therefore, all qhmap commands would have to be run for each new HDL design.

For Verilog users, the compilation commands that need to be executed are:


qhlib $VERILOG_DESTN/simprim
qhmap simprim $VERILOG_DESTN/simprim
qvlcom -work simprim $XILINX/verilog/data/*.vmd


(none required)


qhlib $VERILOG_DESTN/uni3000
qhmap uni3000 $VERILOG_DESTN/uni3000
qvlcom -work uni3000 $XILINX/verilog/src/UNI3000/*.v

qhlib $VERILOG_DESTN/uni4000e # Not included in compile script
qhmap uni4000e $VERILOG_DESTN/uni4000e
qvlcom -work uni4000e $XILINX/verilog/src/UNI4000E/*.v

qhlib $VERILOG_DESTN/uni4000x
qhmap uni4000x $VERILOG_DESTN/uni4000x
qvlcom -work uni4000x $XILINX/verilog/src/UNI4000X/*.v

qhlib $VERILOG_DESTN/uni5200
qhmap uni5200 $VERILOG_DESTN/uni5200
qvlcom -work uni5200 $XILINX/verilog/src/UNI5200/*.v

qhlib $VERILOG_DESTN/uni9000 # Not included in compile script
qhmap uni9000 $VERILOG_DESTN/uni9000
qvlcom -work uni9000 $XILINX/verilog/src/UNI9000/*.v

For VHDL users, the commands are:


qhlib $VHDL_DESTN/simprim
qhmap simprim $VHDL_DESTN/simprim
qvhcom -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd
qvhcom -work simprim $XILINX/vhdl/src/simprims/simprim_Vcompoents.vhd
qvhcom -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd


qhlib $VHDL_DESTN/logiblox
qhmap logiblox $VHDL_DESTN/logiblox
qvhcom -work logiblox $XILINX/vhdl/src/logiblox/mvlutil.vhd
qvhcom -work logiblox $XILINX/vhdl/src/logiblox/mvlarith.vhd
qvhcom -work logiblox $XILINX/vhdl/src/logiblox/logiblox.vhd


qhlib $VHDL_DESTN/unisim
qhmap unisim $VHDL_DESTN/unisim
qvhcom -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
qvhcom -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
qvhcom -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
qvhcom -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd

qhlib $VHDL_DESTN/unisim_5k
qhmap unisim_5k $VHDL_DESTN/unisim_5k
qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCOMP52K.vhd
qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL52K.vhd
qvhcom -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCFG52K.vhd

CORE Generator (COREGen must be installed seperatly from M1)

qhlib $VHDL_DESTN/xul
qhmap xul $VHDL_DESTN/xul
qvhcom -87 -work xul $COREGEN/ip/xilinx/xul/ul_utils.vhd

(NOTE: $COREGEN refers to the location in which CORE Generator was installed on the system.)
AR# 2478
Date 10/01/2008
Status Archive
Type General Article