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AR# 24795

LogiCORE Endpoint Block for PCI Express v1.3 - x1 and x2 simulation does not run correctly when core is generated on an NT platform

Description

A x1 and x2 simulation does not run correctly when the core is generated on an NT platform. This problem occurs because some of the signals in the GTP wrapper file are not driven correctly, which causes "x's" to appear in simulation.

Solution

The pcie_gt_wrapper.v file currently generates: 

 

always @(posedge pclk) begin 

if (gtpreset == 1'b1) begin 

gt_rx_power_down_reg = 16'h0;  

gt_pipe_reset_reg = 8'h0; 

gt_rx_polarity_reg = 8'h0; 

gt_rx_data = 63'h0;  

gt_rx_data_k = 8'h0;  

gt_rx_valid = 8'h0;  

gt_rx_elec_idle = 8'hff; 

gt_rx_status = 24'h0;  

gt_rx_phy_status = 8'h0; 

gt_rx_chanisaligned = 8'h0; 

end 

else begin 

gt_rx_power_down_reg = gt_power_down;  

gt_pipe_reset_reg = gt_pipe_reset; 

gt_rx_polarity_reg = gt_rx_polarity; 

gt_rx_data = gt_rx_data_reg;  

gt_rx_data_k = gt_rx_data_k_reg;  

gt_rx_valid = gt_rx_valid_reg;  

gt_rx_elec_idle = gt_rx_elec_idle_reg;  

gt_rx_status = gt_rx_status_reg;  

gt_rx_phy_status = gt_rx_phy_status_reg;  

gt_rx_chanisaligned = gt_rx_chanisaligned_reg; 

end  

end  

 

This is what it should be: 

 

reg [7:0] one = 8'hff; 

 

always @(posedge pclk) begin 

if (gtpreset == 1'b1) begin 

gt_rx_power_down_reg = 16'h0;  

gt_pipe_reset_reg = 8'h0; 

gt_rx_polarity_reg = 8'h0; 

gt_rx_data = 63'h0;  

gt_rx_data_k = 8'h0;  

gt_rx_valid = 8'h0;  

gt_rx_elec_idle = 8'hff; 

gt_rx_status = 24'h0;  

gt_rx_phy_status = 8'h0; 

gt_rxchanisaligned = 8'h0; 

end 

else begin 

gt_rx_power_down_reg[NO_OF_LANES*2-1:0] = gt_power_down[NO_OF_LANES*2-1:0];  

gt_pipe_reset_reg[NO_OF_LANES-1:0] = gt_pipe_reset[NO_OF_LANES-1:0]; 

gt_rx_polarity_reg[NO_OF_LANES-1:0] = gt_rx_polarity[NO_OF_LANES-1:0]; 

gt_rx_data[NO_OF_LANES*8-1:0] = gt_rx_data_reg[NO_OF_LANES*8-1:0];  

gt_rx_data_k[NO_OF_LANES-1:0] = gt_rx_data_k_reg[NO_OF_LANES-1:0];  

gt_rx_valid[NO_OF_LANES-1:0] = gt_rx_valid_reg[NO_OF_LANES-1:0];  

gt_rx_elec_idle[NO_OF_LANES-1:0] = gt_rx_elec_idle_reg[NO_OF_LANES-1:0];  

gt_rx_status[NO_OF_LANES*3-1:0] = gt_rx_status_reg[NO_OF_LANES*3-1:0];  

gt_rx_phy_status[NO_OF_LANES-1:0] = gt_rx_phy_status_reg[NO_OF_LANES-1:0];  

gt_rxchanisaligned[NO_OF_LANES-1:0] = gt_rxchanisaligned_reg[NO_OF_LANES-1:0]; 

gt_rx_power_down_reg[15:NO_OF_LANES*2] = 0;  

gt_pipe_reset_reg[7:NO_OF_LANES] = 0; 

gt_rx_polarity_reg[7:NO_OF_LANES] = 0; 

gt_rx_data[63:NO_OF_LANES*8] = 0;  

gt_rx_data_k[7:NO_OF_LANES] = 0;  

gt_rx_valid[7:NO_OF_LANES] = 0;  

gt_rx_elec_idle[7:NO_OF_LANES] = one[7:NO_OF_LANES];  

gt_rx_status[23:NO_OF_LANES*3] = 0;  

gt_rx_phy_status[7:NO_OF_LANES] = 0;  

gt_rxchanisaligned[7:NO_OF_LANES] = 0; 

end  

end

AR# 24795
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article