This problem is an issue only with ModelSim XE III 6.2c and occurs when a generic is omitted from the generic map in the configuration specification.
To work around this problem, make sure that all entity generics with a default value expression are listed in the generic map configuration expression.
The missing entries can be found by comparing the generics in the behavioral model, which is contained in "%modelsim%/xilinx/vhdl/src/XilinxCorelib," with the behavioral simulation file generated by the CORE Generator.
For example, in the core instantiation below, even though you don't need all the generics, because of its default you will have to declare every single one of those.
entity BLK_MEM_GEN_V2_3_output_stage is generic ( C_DATA_WIDTH : integer := 32; C_HAS_SSR : integer := 1; C_HAS_REGCE : integer := 1; C_HAS_EN : integer := 1; C_FAMILY : string := "virtex5"; sinit_val : std_logic_vector; num_stages : integer := 1; flop_delay : time := 100 ps); port ( CLK : in std_logic; SSR : in std_logic; REGCE : in std_logic; EN : in std_logic; DIN : in std_logic_vector(C_DATA_WIDTH-1 downto 0); DOUT : out std_logic_vector(C_DATA_WIDTH-1 downto 0)); end BLK_MEM_GEN_V2_3_output_stage;
NOTE: This is not limited to just the block RAM Core. The same resolution should be used for all cores that exhibit similar issues.
This issue is scheduled to be fixed with ModelSim XE-III 6.2g, which should be available in ISE 9.2i.