To interface a 32-bit (or larger) differential data bus to the Virtex-5 FPGA via a Clock Capable I/O and a BUFIO requires more than one bank. However, the BUFIO can only access the pins in a single bank. How is this achieved?
In a Virtex-5 device, the BUFIO can clock the IOBs in a single bank which consists of 40 IOBs. If your interface requires more than 40 IOBs, you can use a zero delay clock buffer to replicate the clock and route it to the clock capable I/Os on the additional banks you require.