We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24833

Virtex-5 - How do I clock multiple banks using a single clock?


To interface a 32-bit (or larger) differential data bus to the Virtex-5 FPGA via a Clock Capable I/O and a BUFIO requires more than one bank. However, the BUFIO can only access the pins in a single bank. How is this achieved?


In a Virtex-5 device, the BUFIO can clock the IOBs in a single bank which consists of 40 IOBs. If your interface requires more than 40 IOBs, you can use a zero delay clock buffer to replicate the clock and route it to the clock capable I/Os on the additional banks you require.

AR# 24833
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked