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AR# 24846

LogiCORE Block Memory Generator - "WARNING:PhysDesignRules:1060 - Dangling pins on RAMB16BWER" or "WARNING:PhysDesignRules:1155 - Dangling pins on RAMB16WER"

Description

Keywords: CORE Generator, memory, asynch, asymmetric, nonsymmetric, non-symmetric, block RAM, RAMB, BRAM, RAMB16, RAMB, simulation, UniSim, SimPrim, NetGen, SDF, MAP, BitGen, warning, v2pro, Virtex-4, Spartan-3a

When using the Block Memory Generator Core in a Simple Dual Port RAM configuration, the following warnings can occur when running MAP and BitGen on your design:

The MAP report might contain the following:

"WARNING:PhysDesignRules:1060 - Dangling pins on
block:<U0/ARCH_B.xfft_inst/memories[0].blkmem_gen.dpms/use_blk_mem_gen.i_blk_
mem/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2.ram/dp36x36.ram/U0/ARCH_
B.xfft_inst/memories[0].blkmem_gen.dpms/use_blk_mem_gen.i_blk_mem/blk_mem_gen
erator/valid.cstr/ramloop[0].ram.r/v2.ram/dp36x36.ram.A>:<RAMB16_RAMB16A>.
The block is configured to use input parity pins. There are dangling output
parity pins."

The BitGen report might contain the following:

"WARNING:PhysDesignRules:1060 - Dangling pins on
block:<U0/ARCH_B.xfft_inst/memories[0].blkmem_gen.dpms/use_blk_mem_gen.i_blk_
mem/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2.ram/dp36x36.ram/U0/ARCH_
B.xfft_inst/memories[0].blkmem_gen.dpms/use_blk_mem_gen.i_blk_mem/blk_mem_gen
erator/valid.cstr/ramloop[0].ram.r/v2.ram/dp36x36.ram.A>:<RAMB16_RAMB16A>.
The block is configured to use input parity pins. There are dangling output
parity pins."

Alternatively, the following messages might occur:

MAP report:

"WARNING:PhysDesignRules:1155 - Dangling pins on
block:<U0/ARCH_B.xfft_inst/memories[3].blkmem_gen.dpms/use_blk_mem_gen.i_blk_
mem/blk_mem_generator/valid.cstr/ramloop[0].ram.r/device.ram/ram/U0/ARCH_B.xfft
_inst/memories[3].blkmem_gen.dpms/use_blk_mem_gen.i_blk_mem/blk_mem_generator
/valid.cstr/ramloop[0].ram.r/device.ram/ram>:<RAMB16BWER_RAMB16BWER>. The
block is configured to use input parity pin DIAP0. There is dangling output
for parity pin DOPA0."

BitGen Report:

"WARNING:PhysDesignRules:1155 - Dangling pins on
block:<U0/ARCH_B.xfft_inst/memories[3].blkmem_gen.dpms/use_blk_mem_gen.i_blk_
mem/blk_mem_generator/valid.cstr/ramloop[0].ram.r/device.ram/ram/U0/ARCH_B.xfft
_inst/memories[3].blkmem_gen.dpms/use_blk_mem_gen.i_blk_mem/blk_mem_generator
/valid.cstr/ramloop[0].ram.r/device.ram/ram>:<RAMB16BWER_RAMB16BWER>. The
block is configured to use input parity pin DIAP0. There is dangling output
for parity pin DOPA0."

Solution

This message is reporting that although the DIPA* input ports of RAMB primitives are connected and configured to use the parity bits, the DOPA* output parity bits are left dangling (not used). This is ok to ignore because in the simple dual port configuration, it is possible that the Block Memory Generator core uses true-dual-port ram primitive but uses only port A to write (never to read) and port B to read (never to write). Therefore, the parity bits of unused ports will be unconnected. This issue is known for non Virtex-5 implementation.
AR# 24846
Date Created 09/04/2007
Last Updated 03/01/2007
Status Active
Type General Article