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AR# 24848

LogiCORE Block Memory Generator - Migration Kit Release Note and Known Issues

Description

Keywords: CORE Generator, asynch, asymmetric, nonsymmetric, non-symmetric, block RAM, RAMB, block RAM, BRAM, RAMB16, RAMB, simulation, single, dual, port, block, migrate, scripts, bmg_migrate.pl, recover_xco

The Block Memory Generator LogiCORE (Block Mem Gen) replaces the following two legacy CORE Generator LogiCOREs:

Dual Port Block Memory (v6.x)
Single Port Block Memory (v6.x)

The migration kit is available to convert all the legacy cores to released versions of Block Memory Generator cores. Please download the migration kit and Application Note 917 from:

http://www.xilinx.com/ipcenter/blk_mem_gen/blk_mem_gen_migration_kit.htm

The instructions for using the migration kit are described in the "Block Memory Generator Migration Guide" Application Note (Xilinx XAPP917):
http://www.xilinx.com/support/documentation/application_notes/blk_mem_gen_xapp917.pdf

Solution

Known Issues

- When converting a Single Port Block Memory V6.x with VHDL instantiation to a Block Memory Generator instantiation configured as True Dual Port, some of the "B" ports are tied-off to "0". The ports that are buses (such as addrb) will then fail with a syntax error.

Work-around: Connect the ports to appropriate signals.

- When converting a Single Port Block Memory V6.x with Verilog instantiation to a Block Memory Generator instantiation, some ports are tied off to "0", which should be connected.

Work-around: Connect the ports to appropriate signals.

- When converting a Single Port Block Memory V6.x with VHDL instantiation to a Block Memory Generator instantiation, if the configuration includes input registers, the migration kit constructs a process to registering the inputs for both the A and B inputs. Since the source file is a Single Port memory, the B inputs tie-off the input registers to (others=>'0'), which causes a syntax error.

Work-around: Manually edit the VHDL file to remove unnecessary registers.

- When converting a Single Port Block Memory V6.x with Verilog instantiation to a Block Memory Generator instantiation, the web and dinb ports are tied to "0" because they are not used. However, this causes port width mismatches in simulation.

Work-around: Using intermediate signals of the correct width that are tied to 0's, and then connecting those signals to the ports.

- The recover_xco.pl script reports V2.3. This version number should be removed.

Work-around: Ignore the reported message about v2.3. The script can support the generation of Block Memory Generator v2.4.

- The bmg_migrate.pl migration script always requires a .v or .vhd file and a .xco file, whether or not these files are actually used.

Work-around: Specify a dummy .v or .vhd file in the command line when running the script.
AR# 24848
Date Created 09/04/2007
Last Updated 09/18/2009
Status Active
Type General Article