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AR# 24865

9.1 System Generator for DSP - When I generate a design using "with testbench" the Verilog testbench does not show up in the generated ISE project


When using Verilog as the specified language, if "with testbench" is selected from System Generator during generation, I expect to see a testbench added to the ISE project which is created, but there are no sources added as testbenches.


This is a known issue with the resulting ISE project from System Generator 9.1. The Verilog testbench files are actually added to the project; however, they are added as sources instead of as testbench files.  


This will be fixed in a future version of System Generator.

AR# 24865
Date 05/21/2014
Status Archive
Type General Article
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