We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24866

9.1 System Generator for DSP - Why do I receive the error message "standard exception: XNetlistEngine" when I try to generate a design containing the FIFO block for a Spartan-3E device?


When my design contains a FIFO block and I am targeting a Spartan-3E device, the following error message occurs during generation:

"standard exception: XNetlistEngine:

An exception was raised:

com.xilinx.sysgen.netlist.NetlistInternal: expected to find C:\xprojects\dsp\sysgen_examples\91_known_issues\netlist\sysgen\coregen_dLAR/coregen_tmp/fifo_s50_s3e_2a0b142b480f30ab_flist.txt at C:\xprojects\dsp\sysgen_examples\91_known_issues\netlist\sysgen\masterScript1009.pl line 303

Reported by:



This is because the FIFO block is attempting to use the Synchronous FIFO v5 Core for a device which the core does not support.

You can work around this issue by bringing in the latest FIFO Generator core as a black box or by generating for a different architecture, such as Spartan-3 and then changing the target device back to Spartan-3E in the resulting ISE project.

This is a known issue which will be fixed in a future release of System Generator.

AR# 24866
Date 12/15/2012
Status Active
Type General Article