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AR# 24880

Architecture Wizard 9.1: Spartan 3 family DCM input clock frequency range does not match data sheet


In Architecture Wizard 9.1 the DCM input clock frequency ranges do not match the data sheet. Architecture Wizard will give an error about the input clock frequency range. This error message will not allow a DCM to be generated unless the input clock frequency is within the range given in the error message. Service Pack 3 will fix the range that is checked in the tool. The data sheet values are correct.


This issue is present for ISE 9.1.01i and ISE 9.1.02i. It is fixed in ISE9.1.03i , which was released in late March 2007, and later versions.

To work around this issue, DCMs can be manually instantiated. This is done as follows:

1) In ISE 9.1 select "Edit->Language Templates"

2) Expand either the VHDL or Verilog

3) Expand "Device Primitive Instantiation," "FPGA," "Clock Components," "Digital Clock Manager (DCM)"

4) Select Either the DCM or the DCM_SP, depending on whether you are targeting a Spartan-3 or Spartan 3E/3A respectively

5) Use this as a base template to instantiate the DCM

Valid ranges are documented in the respective data sheets for the Spartan-3/3E/3A/3AN. The particular section to look for this documentation is under "Switching Characteristics"->"Digital Clock Manager (DCM) Timing."

Alternative method:

1) Enter a range that Architecture Wizard accepts as valid (above 32 MHz).

2) Proceed entering parameters as desired.

3) If you would like to use the CLKFX output enter a value of 2 for multiply and 1 for divide.

4) Generate the DCM.

5) Open the created VHD/V file and modify the instantiation generic map (not the component declaration) in the case of a VHDL generation, or the defparams in the case of Verilog.

5.1) Make sure that the CLKIN_PERIOD is set to the proper value for the input clock frequency desired.

5.2) Set the CLKFX_MULTIPLY and CLKFX_DIVIDE parameters are set to the values desired for the output frequency and within the limits specified in the DC and Switching Characteristics for the part targeted.

6) Save the modified VHD/V file under a new filename.

7) Add the modified VHD/V file to the project.

8) Use the instantiation template to instantiate the modified DCM module in your design.

AR# 24880
Date 12/15/2012
Status Active
Type General Article
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