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AR# 24883

11.1 EDK - Two Data Side OCM block RAM controllers connected to the same OCM bus do not work correctly

Description

I have two Data Side OCM BRAM controllers in my design connected on the same OCM bus. When I write to one block RAM, the same data is written to another block RAM as well. How can I solve this problem?

Solution

The data-side block RAM controller ("dsbram_if_cntlr") is configured by default to acknowledge all D-OCM transactions irrespective of the address placed on the address bus by the processor. This is also done for performance reasons, to eliminate the need for the block RAM controller to check the address bus, in situations where the block RAM controller is the only peripheral on the OCM bus. When adding peripherals to the OCM bus, this feature must be disabled by setting the C_RANGECHECK parameter on each block RAM controller, as shown below:

BEGIN dsbram_if_cntlr

PARAMETER INSTANCE = docm_cntlr

PARAMETER HW_VER = 3.00.a

PARAMETER C_BASEADDR = 0x20880000

PARAMETER C_HIGHADDR = 0x20883fff

PARAMETER C_RANGECHECK = 1

BUS_INTERFACE DSOCM = docm

BUS_INTERFACE PORTA = dsocm_porta

END

AR# 24883
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article