When I constrain parts of my design using a FROM ... TO constraint, the number of paths analyzed is larger than when this part is covered with a PERIOD constraint but the number of Unconstrained Paths does not increase.
Why does this occur?
The destination TIMEGRP for the FROM ... TO constraint probably contains distributed Dual-Port Synchronous RAMs.
Paths to this RAM are both synchronous and asynchronous; e.g., the path to the data input (D) is synchronous but the paths to the read address inputs (DPRA) are asynchronous.
A PERIOD will constrain only synchronous paths but a FROM ... TO will constrain both the synchronous and asynchronous paths to this RAM.
For example, a path from an FF to the D input of this RAM is a synchronous path constraining the data pin setup to clock and would be covered by a PERIOD or a FROM ... TO constraint.
A path from an FF to the DPRA input of this RAM is an asynchronous path to the read address input and would be covered only by a FROM ... TO constraint.
In addition, the second path also traces through the RAM and ends at another endpoint; e.g., an FF.
If the destination FF and RAM are both contained in the destination TIMEGRP of the FROM ... TO constraint, both are analyzed by the FROM ... TO but only the latter would be analyzed by the PERIOD constraint. Therefore, the number of analyzed paths for a FROM ... TO constraint is larger.
As this path fully contains the shorter path to the read address input, it is not seen as unconstrained and therefore does not occur in the Unconstrained Paths section in the timing report.