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AR# 24947

9.1i Timing - Feedback compensation is incorrect for PLL2DCM and DCM2PLL components


In the design, I have PLL2DCM and DCM2PLL components, but the feedback delay through these components appears to be incorrect.

When is this going to be fixed?


This problem has been fixed in the latest 9.1i Service Pack available at:

The first service pack containing the fix is 9.1i Service Pack 3.

AR# 24947
Date 01/18/2010
Status Archive
Type General Article
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