This README Answer Record contains the Release Notes for 9.1i Service Packs.
The Release Notes include installation instructions and a list of the issues that have been fixed. EDK Service Packs are cumulative; for example, fixes in Service Pack 1 are also included in Service Pack 2.
NOTE: EDK 9.1i sp1 requires ISE 9.1i sp2 or later, and EDK 9.1i sp2 requires ISE 9.1i sp3
A successful installation of Xilinx EDK 9.1i Service Pack "x" updates your software version number to 9.1.0xi.
NOTES: - The destination directory specified during the setup operation must contain an existing Xilinx EDK installation. Only existing files are updated. - You must set the XILINX and XILINX_EDK environment variables before installing the Service Pack.
9.1i EDK - ERROR:MDT - Given value for Parameter RS232_Uart:C_CLK_FREQ - system.mhs line 184 is = 75000000 (Xilinx Answer 25132) 9.1i EDK - There is no serial output on the terminal after downloading the VxWorks image (Xilinx Answer 25125) 9.1i EDK - SDK - Error: "make: *** No rule to make target 'C:/Test/src/Test.ld', needed by 'Test.elf' " (Xilinx Answer 25071) 9.1i EDK - "Warning: Attribute Syntax Warning The attribute FACTORY_JF on DCM_ADV instance * is set to 1100000010000000." (Xilinx Answer 25042) 9.1i EDK - I cannot compile Linux 2.6 for my EDK project (Xilinx Answer 24997) 9.1i EDK - The VxWorks BSP is not being built on Linux and Solaris (Xilinx Answer 22286) 9.1i EDK - PLB memory addresses are not accessible to debug interface ("ERROR (1059): I-Side Memory Access Check Failed") (Xilinx Answer 25015) 9.1i EDK - TestApp_Memory sample design does not pass on the ML501 board (Xilinx Answer 24989) 9.1i EDK - A successful download of my software application through XMD gives an incorrect memory map (Xilinx Answer 25133) 9.1i EDK - The ML505 board reads the GPIO DIP switch in bit-reverse order (Xilinx Answer 25134) 9.1i EDK - OPB_MDM v2.00.a - MDM clock must be twice as fast as System ACE clock for ELF load (Xilinx Answer 23736) 9.1i EDK SP2, 'mch_opb_ddr2_v1_L_a ' Read Data Comparison Error in mch_opb_ddr2_v1_01_a (Xilinx Answer 25178) 9.1i EDK SP2 - 'mch_opb_emc_v1_01_a', Post Par Simulation fails with timing Error (Xilinx Answer 25181) 9.1i EDK SP2 - 'plb_ddr2_v1_01_a', The pbl_ddr2 in Asynch mode is generating timing errors on signals that have separate clock domains (Xilinx Answer 25185)