Spartan-3A and Virtex-5 PCI designs that met timing in 9.1i sp2 fail timing in 9.1i SP3. Why does this happen?
Pre-production speed files for Spartan-3A and Virtex-5 have continued to evolve in ISE 9.1i Service Pack 3. As a result, PCI 66 MHz designs that met timing using IP update 1 under 9.1i sp2 might fail timing under sp3. Because these designs are routed using exact-mode DIRT constraints, PAR is unable to readjust critical paths to accommodate the new speed-file data.
IP update 3 with a planned mid-May release will bring PCI 66 MHz implementations for these two families in line with sp3 speed files. For immediate help on this, please open a case with the Support team at: