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AR# 25051

9.1i Virtex-5 PAR - What are the rules for IDELAYCTRL replication and optimization?

Description

Keywords: IDELAYCTRL, replication, constraints, optimization

The Virtex-5 User Guide (UG190) has the following description of how the implementation tools handle IDELAYCTRL components. It mentions that IDELAYCTRLs are replicated if they are not constrained. What are the rules for this replication?
(See "IDELAYCTRL Usage and Design Guidelines", under the IDELAYCTRL Overview):
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides

"Instantiating IDELAYCTRL Without LOC Constraints
When instantiating IDELAYCTRL without LOC constraints, the user must instantiate only
one instance of IDELAYCTRL in the HDL design code. The implementation tools autoreplicate
IDELAYCTRL instances throughout the entire device, even in clock regions not
using the delay element. This results in higher power consumption due to higher resource
utilization, the use of one global clock resource in every clock region, and a greater use of
routing resources. The signals connected to the RST and REFCLK input ports of the
instantiated IDELAYCTRL instance are connected to the corresponding input ports of the
replicated IDELAYCTRL instances."

Solution

There are several use cases for unconstrained IDELAYCTRL components:

Case 1- One unconstrained, instantiated IDELAYCTRL - The IDELAYCTRL is replicated to all clock regions and then, after placement, the unused IDELAYCTRLs are optimized away from the clock regions where they are not needed.

Case 2 - More than one IDELAYCTRL is instantiated, and one IDELAYCTRL is unconstrained - The unconstrained IDELAYCTRL is replicated to fill out all clock regions in the device and then, after placement, the unused IDELAYCTRLs are optimized away from the clock regions where they are not needed.

Case 3 - More than one IDELAYCTRL is instantiated, and more than one IDELAYCTRL is unconstrained - MAP will error out.

NOTE: The optimization of unused IDELAYCTRL components was temporarily disabled in ISE version 8.2isp3 to avoid a problem that could occur due to the optimization. The optimization was then re-enabled in ISE version 9.1isp1.

AR# 25051
Date Created 09/04/2007
Last Updated 10/13/2008
Status Active
Type General Article