We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25100

MIG v1.7 - Is it possible to use only one 40-pin bank in a Virtex-5 device for a 36-bit QDR2 SRAM controller?


Keywords: QDR2, QDRII, Virtex-5, bank, 40, 36-bit

A bank in a Virtex-5 device contains 40 I/Os. The Xilinx Virtex-5 QDRII controller uses the following pins for a x36 interface:
- 36 bits of data
- 2 clocks
- 2 Vrefs
- VRP/VRN pins for DCI

Thus, the maximum limit of 40 pins per bank is exceeded. Because of this, Xilinx recommends using 2 banks each with 18 data bits where CQ_P is used to capture the first set of bits in one bank, while CQ_N is used to capture the remaining data bits in the adjacent bank.

Is there any way to modify the MIG output UCF to fit the x36 interface into a single 40-pin bank?


Based on whether DCI is necessary, one of the following can be used to fit a x36 QDRII interface in one Virtex-5 bank:

1. If DCI is not needed, the VRN/VRP I/Os can be used for the QDRII interface. Turn off DCI within the MIG GUI and allow the tool to generate a pin-out using one bank for the 36-bit read data. DCI will not be used for the inputs. However, the termination scheme for the Q and CQ signals at the FPGA end will need to be determined based on IBIS simulations.

2. If DCI is needed, you can use the Virtex-5 DCI Cascading feature. Information on this feature is provided in the Virtex-5 User Guide > SelectIO Resources > Virtex-5 Digitally Controlled Impedance (DCI) > DCI Cascading. The "Virtex-5 User Guide" (UG190) can be found at:

Usage of this feature is described in the Constraints Guide > Chapter 5: Xilinx Constraints > DCI_CASCADE. The Constraints Guide can be found at:

To use this option, again turn off DCI within the MIG GUI and allow the tool to generate a pin-out using one bank. Then, follow the above documentation to enable DCI Cascade by assigning Vrp/Vrn pins for the Master bank.

NOTE: Starting with MIG 2.0, the QDR II SRAM pin-out guidelines have been modified so that a x36 interface can fit into one Virtex-5 bank. MIG will now generate a pin-out with the interface located in one bank.
AR# 25100
Date 04/06/2009
Status Archive
Type General Article
Page Bookmarked