The ML555 board ships with a 32-bit 33 MHz PCI bus reference design loaded in one of the two Platform Flash devices on the board. The reference design uses one of the programmable clock synthesizers on the ML555 to generate a 200 MHz reference clock for the IDELAYCTRL reference clock. Although the FPGA is configured and the DONE LED is illuminated on the board, occasionally the clock synthesizer does not initialize properly on the ML555 board, which prevents the ML555 from being recognized in a PCI bus scan in the system unit.
Question 1: How can I obtain a new MCS file for the ML555 board?
Question 2: I am creating my own design using ISE 8.2.03i. What edits are needed to the UCF generated with the core to use the onboard oscillator?
Question 3: I am creating my own design using ISE 9.1.03. What edits are needed to the UCF generated with the core to use the onboard oscillator?
Solution for Question 1
1. Download a new MCS file for the ML555 board that contains a new PCI32 reference design. This design uses the free running 200 MHz LVPECL oscillator on the ML555 board. The programmable clock synthesizer is not used in the updated design.
2. Download the corrected MCS and other necessary files from:
3. See the ML555 UG201 for instructions on how to configure the FPGA using the Xilinx iMPACT tool. The new design contains a PCI32 design in image 0 and a PCIX-133 design in image 1. The second Platform Flash should be loaded with the new MCS file.
4. If you have started your own PCI32 design based upon ISE 8.2.03i with IP Update 3, you can modify the UCF file to use the free running 200 MHz LVPECL oscillator on the ML555 instead of the clock synthesizer.
Solution for Question 2
To change from clock synthesizer to free running 200 MHz LVPECL oscillator on the ML555, edit the UCF file generated by the CORE Generator as follows:
1. Navigate to the CORE Generator PCI32 design directory and then to the "example_design" subdirectory.
2. Open the "pci32_v4_1_top.ucf" file.
3. Find the "Additional User Constraints" section near the bottom of the file. Edit the "RCLK_P" and "RCLK_N" constraints as shown below:
NET "RCLK" PERIOD = 5.000;
NET "RCLK_P" LOC = "K17" | IOSTANDARD = LVPECL_25;
NET "RCLK_N" LOC = "L18" | IOSTANDARD = LVPECL_25;
4. Re-implement the design. Design will now use a free running 200 MHz clock generated from onboard oscillator.
Solution for Question 3
CORE Generator outputs a default UCF that has RCLK_P and RCLK_N using an I/O standard of LVDS_25. The UCF must be edited because the onboard oscillator uses LVPECL_25. The constraints in the UCF should look as shown in Solution 2 . The I/O standard is the only required changed from the default UCF when using 9.1i software.