UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25120

12.1 Timing Virtex-5 - Why is my OFFSET OUT constraint of ODDR falling group ignored?

Description


I have an ODDR output port in my design, and I have defined separate OFFSET OUT constraints for both rising and falling groups:
 

NET "CLK" TNM_NET = CLK; 
TIMESPEC TS_CLK = PERIOD "CLK" 10 ns; 
TIMEGRP CLK_RISE = RISING CLK; 
TIMEGRP CLK_FALL = FALLING CLK; 
OFFSET = OUT 10.0 ns AFTER "CLK" TIMEGRP CLK_RISE; 
OFFSET = OUT 15.0 ns AFTER "CLK" TIMEGRP CLK_FALL; 
But, the OFFSET OUT constraint for the falling group is ignored during timing analysis. 
WARNING:Timing:3224 - The clock CLK associated with OFFSET = OUT 15 ns AFTER 
COMP "CLK" TIMEGRP CLK_FALL; does not clock any registered output components. 
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 15 ns AFTER COMP "CLK" 
TIMEGRP CLK_FALL; ignored during timing analysis. 
This can be reproduced only for Virtex-5, not for Virtex-4 and other devices.

Solution


For Virtex-4 devices, the Flip-Flops (FF) inside ODDR (OLOGIC) can be taken as separate rising and falling Flip-Flops, so the timing analysis reports different paths for the rising group and falling group.

This is the recommended method. 
 


================================================================================ 
Timing constraint: OFFSET = OUT 10 ns AFTER COMP "CLK" TIMEGRP CLK_RISE; 
 
1 item analyzed, 0 timing errors detected. 
Minimum allowable offset is 9.245ns. 
-------------------------------------------------------------------------------- 
Slack: 0.755ns (requirement - (clock arrival + clock path + data path + uncertainty)) 
Source: ODDR_inst/FF0 (FF) 
Destination: DOUT (PAD) 
Source Clock: CLK_BUFGP rising at 0.000ns 
Requirement: 10.000ns 
Data Path Delay: 4.104ns (Levels of Logic = 1) 
Clock Path Delay: 5.141ns (Levels of Logic = 2) 
Clock Uncertainty: 0.000ns 
Clock Path: CLK to ODDR_inst/FF0 
Location Delay type Delay(ns) Physical Resource 
Logical Resource(s) 
------------------------------------------------- ------------------- 
W9.I Tiopi 0.919 CLK 
CLK 
CLK_BUFGP/IBUFG 
BUFGCTRL_X0Y0.I0 net (fanout=1) 0.835 CLK_BUFGP/IBUFG 
BUFGCTRL_X0Y0.O Tbgcko_O 0.900 CLK_BUFGP/BUFG 
CLK_BUFGP/BUFG 
OLOGIC_X2Y12.CLK net (fanout=3) 2.487 CLK_BUFGP 
------------------------------------------------- --------------------------- 
Total 5.141ns (1.819ns logic, 3.322ns route) 
(35.4% logic, 64.6% route)  
Data Path: ODDR_inst/FF0 to DOUT 
Location Delay type Delay(ns) Physical Resource 
Logical Resource(s) 
------------------------------------------------- ------------------- 
OLOGIC_X2Y12.OQ Tockq 0.585 DOUT_OBUF 
ODDR_inst/FF0 
ODDR_inst 
T3.O net (fanout=1) 0.002 DOUT_OBUF 
T3.PAD Tioop 3.517 DOUT 
DOUT_OBUF 
DOUT 
------------------------------------------------- --------------------------- 
Total 4.104 ns (4.102 ns logic, 0.002 ns route) 
(100.0% logic, 0.0% route) 
 
-------------------------------------------------------------------------------- 


 

================================================================================ 
Timing constraint: OFFSET = OUT 15 ns AFTER COMP "CLK" TIMEGRP CLK_FALL; 
 
1 item analyzed, 0 timing errors detected. 
Minimum allowable offset is 14.245 ns. 
-------------------------------------------------------------------------------- 
Slack: 0.755ns (requirement - (clock arrival + clock path + data path + uncertainty)) 
Source: ODDR_inst/FF2 (FF) 
Destination: DOUT (PAD) 
Source Clock: CLK_BUFGP falling at 5.000ns 
Requirement: 15.000ns 
Data Path Delay: 4.104ns (Levels of Logic = 1) 
Clock Path Delay: 5.141ns (Levels of Logic = 2) 
Clock Uncertainty: 0.000ns  
Clock Path: CLK to ODDR_inst/FF2 
Location Delay type Delay(ns) Physical Resource 
Logical Resource(s) 
------------------------------------------------- ------------------- 
W9.I Tiopi 0.919 CLK 
CLK 
CLK_BUFGP/IBUFG 
BUFGCTRL_X0Y0.I0 net (fanout=1) 0.835 CLK_BUFGP/IBUFG 
BUFGCTRL_X0Y0.O Tbgcko_O 0.900 CLK_BUFGP/BUFG 
CLK_BUFGP/BUFG 
OLOGIC_X2Y12.CLK net (fanout=3) 2.487 CLK_BUFGP 
------------------------------------------------- --------------------------- 
Total 5.141ns (1.819ns logic, 3.322ns route) 
(35.4% logic, 64.6% route) 
 
Data Path: ODDR_inst/FF2 to DOUT 
Location Delay type Delay(ns) Physical Resource 
Logical Resource(s) 
------------------------------------------------- ------------------- 
OLOGIC_X2Y12.OQ Tockq 0.585 DOUT_OBUF 
ODDR_inst/FF2 
ODDR_inst 
T3.O net (fanout=1) 0.002 DOUT_OBUF 
T3.PAD Tioop 3.517 DOUT 
DOUT_OBUF 
DOUT 
------------------------------------------------- --------------------------- 
Total 4.104ns (4.102ns logic, 0.002ns route) 
(100.0% logic, 0.0% route) 
-------------------------------------------------------------------------------- 


However, for Virtex-5 devices there is a small change regarding the physical resource.

The OUTFF instance is a BEL inside the OLOGIC, which can be configured as a Latch, FF, or ODDR.
So ODDR is the smallest physical resource shown in the timing report.
It is not necessary to take it as an element with both rising and falling registers.

Only 1 OFFSET OUT constraint is required for such an instance.
For the falling-edge data path, the constraint requirement and clock arrival time will be auto-adjusted.  
 


================================================================================ 
Timing constraint: OFFSET = OUT 10 ns AFTER COMP "CLK" TIMEGRP CLK_RISE; 
1 item analyzed, 0 timing errors detected. 
Minimum allowable offset is 7.344 ns. 
-------------------------------------------------------------------------------- 
Slack: 2.656ns (requirement - (clock arrival + clock path + data path + uncertainty)) 
Source: ODDR_inst (FF) 
Destination: DOUT (PAD) 
Source Clock: CLK_BUFGP rising at 0.000ns 
Requirement: 10.000ns 
Data Path Delay: 3.228ns (Levels of Logic = 1) 
Clock Path Delay: 4.091ns (Levels of Logic = 2) 
Clock Uncertainty: 0.025ns  
Clock Path: CLK to ODDR_inst 
Location Delay type Delay(ns) Physical Resource 
Logical Resource(s) 
------------------------------------------------- ------------------- 
R11.I Tiopi 0.818 CLK 
CLK 
CLK_BUFGP/IBUFG 
BUFGCTRL_X0Y12.I0 net (fanout=1) 1.304 CLK_BUFGP/IBUFG 
BUFGCTRL_X0Y12.O Tbgcko_O 0.250 CLK_BUFGP/BUFG 
CLK_BUFGP/BUFG 
OLOGIC_X0Y74.CLK net (fanout=2) 1.719 CLK_BUFGP 
------------------------------------------------- --------------------------- 
Total 4.091ns (1.068ns logic, 3.023ns route) 
(26.1% logic, 73.9% route)  
Data Path: ODDR_inst to DOUT 
Location Delay type Delay(ns) Physical Resource 
Logical Resource(s) 
------------------------------------------------- ------------------- 
OLOGIC_X0Y74.OQ Tockq 0.607 DOUT_OBUF 
ODDR_inst 
L14.O net (fanout=1) 0.000 DOUT_OBUF 
L14.PAD Tioop 2.621 DOUT 
DOUT_OBUF 
DOUT 
------------------------------------------------- --------------------------- 
Total 3.228ns (3.228ns logic, 0.000ns route) 
(100.0% logic, 0.0% route) 
-------------------------------------------------------------------------------- 


For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug612.pdf
 
AR# 25120
Date Created 09/04/2007
Last Updated 12/02/2014
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less