This Release Note and Known Issues Answer Record is for the LogiCORE Endpoint Block for PCI Express v1.4 released in 9.1i IP Update 3, and contains the following:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24847).
As of 9.1i sp 2 IP Update 1 Release, the LogiCORE Endpoint Block for PCI Express requires a license to generate and implement the core. There is no charge for this license. To obtain the license, visit the product lounge at:
- Support added for VCS simulation and VHDL test bench
- Example design supports 64-bit memory access
- Maximum frequency of example design increased to 250MHz
-CR434009: Fixed simulation problem where unused signals were not correctly tied off in the pcie_gt_wrapper.v file. The signals are now correctly tied off.
-CR438475: Fixed wrong path reference in the implementation script files. Path to unisim_comp.v is now correct.
- Refer to the "release_notes.txt" file delivered with the core for known issues at the time of the release.
- See (Xilinx Answer 24795) for information regarding simulation problems due to signals incorrectly tied off in the GT wrapper file.