This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target v3.162 for PCI released in 9.1i IP Update 3, and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24847).
The LogiCORE PCI v3.161 supports only Virtex-4, Spartan-3, and older architectures. For Virtex-5 devices, use the v4.2 PCI Core. For more information on this core, refer to (Xilinx Answer 25165).
When migrating from CORE Generator 8.1i to 9.1i IP Update 1 and later, new licenses are required for the LogiCORE Initiator/Target v3.161 and later for PCI. For more information, see (Xilinx Answer 24718).
- See (Xilinx Answer 22921) for general information regarding timing closure in Virtex-4 devices.
- XC3S700A device support
- XC3S1400A design files updated for ISE 9.1i Service Pack 3
- Verilog synthesis meta-comments updated to Verilog-2001 syntax
- CR 436087: Fixed reported error "ERROR:sim:49 - Couldn't open .../doc/pci64_release_notes.txt for reading".
- Refer to the release notes text file delivered with the core for known issues at the time of the release.
-The name of this core has changed in v3.1.162, so if the user attempts to port old XCO files to v3.1.162, the following setting needs to be changed:
SELECT PCI_64-bit_Interface family Xilinx,_Inc. 3.161 [old]
SELECT LogiCORE_64-bit_Initiator/Target_for_PCI_(Spartan,_Virtex-4_and_older_only) family Xilinx,_Inc. 3.162
- See (Xilinx Answer 25217) regarding duplicated PCI core entries in the CORE Generator taxonomy list.