This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target v5.162 for PCI-X released in 9.1i IP Update 3, and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24847).
The LogiCORE PCI v5.161 supports Virtex-4, Virtex-II Pro, and Virtex-E architectures only. For Virtex-5 devices, use the v6.2 PCI-X Core. For more information on this core, refer to (Xilinx Answer 25167).
When migrating from CORE Generator 8.1i to 9.1i IP Update 1 and later, new licenses are required for the LogiCORE Initiator/Target v5.162 and later for PCI-X. For more information, see (Xilinx Answer 24718).
- Virtex-4 design files updated for ISE 9.1i Service Pack 3
- Verilog synthesis meta-comments updated to Verilog-2001 syntax
- Refer to the release notes text file delivered with the core for known issues at the time of the release.
- The name of this core has changed in v5.1.162, so if you attempt to port old XCO files to v5.1.162, the following setting must be changed:
SELECT PCI-X/PCI_64-bit_Interface family Xilinx,_Inc. 5.161
SELECT LogiCORE_Initiator/Target_for_PCI-X_(Virtex-4_and_older_only) family Xilinx,_Inc. 5.162