This Release Note and Known Issues Answer Record is for the LogiCORE PCI/PCI-X UCF Generator v2.3 released in 9.1i IP Update 3, and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24847).
- See (Xilinx Answer 22921) for general information regarding timing closure in Virtex-4 devices.
- Spartan-3A device support
CR 435585: Fixed Virtex-5 UCF files to use correct IO standard for RCLK_P and RCLK_N. It now uses IOSTANDARD = LVDS_25.
-CR 435586: In Virtex-5 UCFs the IDELAYCTRL reference clock pins, RCLK_P and RCLK_N, are not locked to specific sites. You must add LOC constraints for these pins.
- See (Xilinx Answer 25217) regarding duplicated PCI core entries in the CORE Generator taxonomy list.
-See (Xilinx Answer 25221) regarding the Version Information file link not working.