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  3. AR# 2517: Exemplar: How to instantiate a pullup or pulldown (Galileo and Leonardo) in VHDL

AR# 2517

Exemplar: How to instantiate a pullup or pulldown (Galileo and Leonardo) in VHDL

Description

How do I instantiate an internal or external pullup/pulldown resistor?

Solution


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Internal Pullup/Pulldown:

---------------------------------------



1. Using component pullup (specify -so=xi4 when using Galileo):



LIBRARY ieee;

USE ieee.std_logic_1164.all;



ENTITY test1 IS

PORT ( inbus_a, inbus_b, inbus_c : IN std_logic;

en_a, en_b, en_c : IN std_logic;

stopit : IN std_logic;

common : IN std_logic;

outbus : OUT std_logic );

END test1;



ARCHITECTURE exemplar OF test1 IS



-- Internal pullup

COMPONENT pullup

PORT ( o: OUT std_logic );

END COMPONENT;



SIGNAL int_bus : std_logic;



BEGIN



u0: pullup PORT MAP (int_bus);



-- RTL description

int_bus <= inbus_a AND stopit WHEN en_a = '1' ELSE 'Z';

int_bus <= inbus_b AND stopit WHEN en_b = '1' ELSE 'Z';

int_bus <= inbus_c AND stopit WHEN en_c = '1' ELSE 'Z';



outbus <= common XOR int_bus;



END exemplar;



2. Using Exemplar's pullup procedure (notice the use of exemplar

_1164 package):



LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY exemplar;

USE exemplar.exemplar_1164.ALL;



ENTITY test2 IS

PORT ( inbus_a, inbus_b, inbus_c : IN std_logic;

en_a, en_b, en_c : IN std_logic;

stopit : IN std_logic;

common : IN std_logic;

outbus : OUT std_logic );

END test2;



ARCHITECTURE exemplar OF test2 IS



SIGNAL int_bus : std_logic;



BEGIN



pullup(int_bus);



-- RTL description

int_bus <= inbus_a AND stopit WHEN en_a = '1' ELSE 'Z';

int_bus <= inbus_b AND stopit WHEN en_b = '1' ELSE 'Z';

int_bus <= inbus_c AND stopit WHEN en_c = '1' ELSE 'Z';



outbus <= common XOR int_bus;



END exemplar;





---------------------------------------

External Pullup/Pulldown:

---------------------------------------



1. Using attribute:



LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY exemplar;

USE exemplar.exemplar_1164.ALL;



ENTITY test2 IS

PORT ( inbus_a, inbus_b, inbus_c : IN std_logic;

en_a, en_b, en_c : IN std_logic;

stopit : IN std_logic;

common : IN std_logic;

outbus : OUT std_logic );

ATTRIBUTE pull: STRING;

ATTRIBUTE pull OF inbus_a: SIGNAL is "pullup";

ATTRIBUTE pull OF inbus_b: SIGNAL is "pulldn";

END test2;



ARCHITECTURE exemplar OF test2 IS



SIGNAL int_bus : std_logic;



BEGIN



pullup(int_bus);



-- RTL description

int_bus <= inbus_a AND stopit WHEN en_a = '1' ELSE 'Z';

int_bus <= inbus_b AND stopit WHEN en_b = '1' ELSE 'Z';

int_bus <= inbus_c AND stopit WHEN en_c = '1' ELSE 'Z';



outbus <= common XOR int_bus;



END exemplar;



2. Using control file:



LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY exemplar;

USE exemplar.exemplar_1164.ALL;



ENTITY test2 IS

PORT ( inbus_a, inbus_b, inbus_c : IN std_logic;

en_a, en_b, en_c : IN std_logic;

stopit : IN std_logic;

common : IN std_logic;

outbus : OUT std_logic );

END test2;



ARCHITECTURE exemplar OF test2 IS





SIGNAL int_bus : std_logic;



BEGIN



pullup(int_bus);



-- RTL description

int_bus <= inbus_a AND stopit WHEN en_a = '1' ELSE 'Z';

int_bus <= inbus_b AND stopit WHEN en_b = '1' ELSE 'Z';

int_bus <= inbus_c AND stopit WHEN en_c = '1' ELSE 'Z';



outbus <= common XOR int_bus;



END exemplar;





Control file:



SET inbus_a pull pullup

SET inbus_b pull pulldn
AR# 2517
Date 12/08/2011
Status Archive
Type General Article
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