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AR# 25232

MIG v1.7/v1.72 - Virtex-5 DDR2 MIG design is stuck in Stage-3 calibration in timing simulation and hardware


Keywords: DDR2, SDRAM, Memory Interface Generator, failure, 1.7, 1.72

When I use the MIG design for Virtex-5 DDR2 SDRAM, the first and second stages of calibration complete successfully. However, the controller seems to hang or get stuck in the third stage (read enable) of calibration. This is observed in both timing simulation and hardware.


In the MIG 1.7/1.72 releases, there is a problem with the calibration logic that causes DQS and DQ not to align properly during the first stage of calibration. This causes problems during the third stage of calibration where the design might hang. This issue is seen more often in designs running at higher frequencies.

To resolve this issue, changes are required in the "phy_calib.v/.vhd" file. These changes are included in the MIG 1.73 release which is available through 9.2i IP Update 1. Please see (Xilinx Answer 25406) for information on the MIG 1.73 release and (Xilinx Answer 25222) for informaiton on downloading 9.2i IP Update 1.

If migrating to MIG 1.73 is not feasible, please open a Web Case and request the "phy_calib.v/.vhd" file noted in (Xilinx Answer 25232). To open a Web Case, go to:

AR# 25232
Date 04/06/2009
Status Archive
Type General Article