We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25261

MIG v1.72 - The Virtex-5 DDR2 SDRAM controller does not leave up to four banks open in simulation when the MULTI_BANK_ENABLE parameter is set to 1


Keywords: Memory Interface Generator

When simulating the Virtex-5 DDR2 SDRAM controller with the MULTI_BANK_EN parameter enabled, the simulation does not show up to four banks opened at a time. It continually shows precharges and behaves as though it does not support bank management. How do I fix this so that my simulation properly reflects leaving four banks open at a time?


The problem is with the way some simulators compile the rtl code. This does not have an affect on the behavior in hardware. To resolve the issue and properly simulate leaving up to four banks open at a time, modify the declaration of the MULTI_BANK_EN parameter in all provided MIG rtl files that use this parameter.

The parameter is specified as follows in the provided MIG rtl code:
parameter MULTI_BANK_EN = 1

To work around this compilation issue, declare the parameter as:
parameter MULTI_BANK_EN = 1'b1

This has been modified in the MIG v1.73 release, which is available through 9.2i IP Update 1. For information on downloading 9.2i IP Update 1, see (Xilinx Answer 25222). For information on the MIG v1.73 release, see (Xilinx Answer 25406).
AR# 25261
Date 04/06/2009
Status Archive
Type General Article