AR# 2527: XC4000E: Clarification about the IOB diagram specified on the data book
XC4000E: Clarification about the IOB diagram specified on the data book
Keywords: CE, IK, Tecik, Tecikd, nodelay, IOB
Why are there two specs for Clock Enable to Clock delay (Tecik) for the IOBs, one with delay added and the other without delay added? How can this be possible if only the D input of the flip flop can be set to either delay or nodelay according the data book description of the IOB?
In the 4000 family the clock enable of any flip flop is modeled as a controller of a 2 to 1 mux muxing either the D or the Q of the input flip flop in the IOB. In reality, the controller that sets the signal to either delay or nodelay is on the output of this mux. As a consequence, the delay/no-delay setting affects both the data and the clock enable signal going to the input flip flop of the IOB.
On the other hand, the 4000EX/XL/XV devices only have the delay/nodelay mux on the D signal.