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AR# 25293

9.1i EDK - Simulation MB on S3A fails with "Error: Both DATA_WIDTH_A and DATA_WIDTH_B can not be 0"

Description

Keyword: EDK, simulation, MicroBlaze, Spartan-3A, S3A, data width, 0

When simulating an EDK S3A design, I receive the following error when running the simulation.

I am using the latest SP for both EDK/ISE. ModelSim PE 6.1e.

Error:

-------

# ** Failure: Attribute Syntax Error: Both DATA_WIDTH_A and DATA_WIDTH_B can not be 0.

# Time: 0 ps Iteration: 0 Process: /system/lmb_bram/lmb_bram/ramb16bwe_7/prcs_initialize File: C:/xilinx/ISE_91/vhdl/src/unisims/unisim_VITAL.vhd

# Break at C:/xilinx/ISE_91/vhdl/src/unisims/unisim_VITAL.vhd line 175853

Solution

The problem is in the memory initialization file "system_init.vhd" and will be fixed in EDK 9.2i.

As a work-around, please manually set the data width in the "system_init.vhd" file (example below).

for ramb16bwe_0 : ramb16bwe

use entity unisim.ramb16bwe(ramb16bwe_v)

generic map(

DATA_WIDTH_A => DATA_WIDTH_A,

DATA_WIDTH_B => DATA_WIDTH_B,

INIT_00 => X"FB022F23BE89B33BBF3E3BEF33BEE89FBBF3EB28B33300000000000B000B0B0B",

Also, a fix has been made to the "ucf2vhdl.pl" script which creates the memory initialization file. This file can be downloaded from:

http://www.xilinx.com/txpatches/pub/swhelp/ise9_updates/91i_sp2_edk_ucf2vhdl.zip

AR# 25293
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article