For other architectures, the default in ProjNav for - pr <Pack Registers/Latches into IOBs> was "both," but for Virtex-5 it has been changed to "none." Why is Virtex-5 being treated differently?
Note: This issue involves the default ProjNav option settings for MAP. Option settings are not the same thing as default MAP behavior.
This difference in default options was intentional and will be continued for future new architectures. The decision has to do with the trade off between packing more into the FPGA and achieving faster internal clock frequencies. It was decided to set the default to off for new architectures (e.g., V5) and leave the defaults unchanged for existing architectures in order to not affect existing design behavior.