We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25416

9.1i MAP - ERROR:MapLib:87 - There are invalid FMAPs in the design. See warnings section in MAP report for details of FMAP problems


Key words: FMAP, keep hierarchy

I see the following error during MAP. What is an FMAP, and why does this error occur?

"ERROR:MapLib:87 - There are invalid FMAPs in the design. See warnings section in map report for details of FMAP problems."

FMAPs are symbols that are sometimes used by synthesis tools and core developers to define the contents of a particular Slice LUT. The input/output pins of the FMAP are connected in parallel to the logical symbols that are intended to be mapped into the LUT. Errors occur when the logic constrained cannot be successfully mapped into the LUT.

These errors can occur due to invalid use of the FMAP, but they can also occur due to improper handling of the design by MAP. Two problem areas have been seen:

- The Global Optimization algorithm has been known to change logic so that the FMAP directed packing is invalid.

- Trimming bugs related to KEEP HIERARCHY constraints can invalidate FMAPs. (Xilinx Answer 23990)


If Global Optimization is in use, try running MAP without this option. This problem is currently under investigation.

The KEEP HIERARCHY trimming problem will be fixed in ISE version 9.2i. Meanwhile, try running MAP with optimization allowed across hierarchy boundaries.

AR# 25416
Date 12/15/2012
Status Active
Type General Article