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AR# 25433

10.1 EDK - How do I generate the system_init.vhd without creating the other simulation files?


For system verification and documentation, I simulate the system and thus the IP core with different software applications (various ELF files). Until now, I always used "Generate simulation HDL files" with EDK to generate the simulation files.

Instead of generating the simulation files for the whole design, can I take the wanted ELF file as an input (and the already generated simulation VHDL file) and generate the system_init.vhd?


You can use Data2MEM in command line to generate the UCF file for your software application (the ELF file).

data2mem -bm "system_sim.bmm" -bd "C:\ae_Xilinx\test_9_1\test_edk4\TestApp_Memory\executable.elf" tag microblaze_0 -u -o u tmpucf.ucf

A Perl script "ucf2vhdl.pl" creates the memory initialization file. For Verilog, it will be ucf2ver.pl.

You can create a batch file similar to the following:

data2mem -bm "system_sim.bmm" -bd "..\..\TestStepperController\executable.elf" tag microblaze_0 -u -o u tmpucf.ucf

xilperl %Xilinx_EDK%\bin\nt\ucf2vhdl.pl tmpucf.ucf system_init2.vhd system system_conf beh


AR# 25433
Date 12/15/2012
Status Active
Type General Article