This Release Notes and Known Issues answer record is for the Virtex-4 RocketIO Wizard v1.5, released in 9.2 IP1, and contains the following information:
- New Features
- Bug Fixes
- Known Issues
* Added software support for ISE 9.2i
* Updated algorithm for RXRCPADJ attribute
* GT11_INIT bug reported in (Xilinx Answer 25469) has been fixed
* CR 301286: Unbonded MGTs in some packages are not reflected in the Wizard
* 64B/66B options have not been tested in hardware. Devices supporting 64B/66B
were not available at development time.
* Multilane protocol files such as XAUI may not turn on all required MGTs in
some packages. If your wrapper is missing lanes, please recustomize your
wrapper and select the needed MGTs on Wizard page 2.
* Wizard page 2 (Placement Customization) allowed selection of unbonded MGTs
on the xc4vfx60 in the ff672 package. MGTs X0Y0, X0Y1, X1Y0, and X1Y1 are
not connected to external pins.
* Configurations using different line rates for TX and RX on the same MGT have
not been thoroughly tested, and may not work.
* Example designs for configurations using different data widths for TX and RX
may not function.
* Be careful to use run lengths supported by your silicon version when
selecting "no encoding"/"no decoding" on Wizard page 3.
* The example designs provide little support for CRC. The wrapper will
configure the CRC blocks, but additional work is required to test and
connect the logic.
* Setting the comma alignment (Wizard page 4) smaller than the data path width
allows incoming data to be aligned to multiple positions. The example design
does not account for this and may indicate errors even though data is being
* The example design does not currently include blocks to demonstrate Channel
Bonding and Clock Correction.
* The GT11 smartmodel will produce RX Disparity errors resulting from rounding
problems for some reference clock periods. If, in simulation, the MGT
wrapper locks successfully but shows numerous disparity errors, edit
testbench/example_tb.v(hd) and increment or decrement the REFCLK period
by 0.01. This is the case for Fibre Channel 2x and 4x; for example, where
the refclk period must be changed from 4.71 ns to 4.7 ns.