This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v4.5 that was released in 9.2i IP Update 1. It includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 25222).
- Support for the ISE 9.2i design tools release has been added.
- The IDELAY component is used in GMII and RGMII PHY standards to meet setup and hold timing. This delay element is now on the clock as well as the data pins. This allows the customer to delay either the clock or the data to meet setup and hold timing. In the example design, the clock has been delayed to prevent added jitter that comes from delaying the data pins (see XAPP707). The constraints for setup and hold timing have been updated to ensure compliance with the appropriate specifications. Please see the Getting Started Guide for more information on these constraints.
- The IDELAY was added to the clock and the data is no longer delayed, to ensure no extra jitter is added to the input path.
- When using the Example Design Local Link RX FIFO incorrect data can be read when toggling rd_dst_rdy_n. For more information and a way to work around this issue, see (Xilinx Answer 29660).
Virtex-4 GT11 init blocks can have glitching if not encoded as one-hot in Synplify. This issue does not effect XST. For more information, see (Xilinx Answer 25469).