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AR# 25444

9.2i MAP, Virtex-4/-5 - Why is there a delay on the input data?

Description

When I target a Virtex-4 or Virtex-5 architecture, the input data is delayed. According to the Constraints Guide, the default value for the IOBDELAY = NONE. Why am I still getting this added delay?

Solution

The Constraints Guide incorrectly describes that the default IOBDELAY is NONE. When using either a Virtex-4 or a Virtex-5 architecture, when not using a DCM or a PLL to capture input data, the IDELAY or IODELAY is used in default mode to increase input path delay to achieve a non-positive hold time. This input path delay can be removed by setting the IOBDELAY = NONE constraint as listed in the Constraints Guide. The documentation will be updated in a future release to clarify this behavior.

This path delay is currently documented in the Virtex-4 and Virtex-5 User Guides under SelectIO Logic Resources, IDELAY, and IODELAY respectively, under zero-hold time delay mode.

Virtex-4 User Guide:

http://www.xilinx.com/bvdocs/userguides/ug070.pdf

Virtex-5 User Guide:

http://www.xilinx.com/bvdocs/userguides/ug190.pdf

AR# 25444
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article