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AR# 25457

LogiCORE SPI-4.2 (POS-PHY L4) v8.4 - Release Notes and Known Issues for 9.2i IP Update 1 (9.2i_IP1)

Description

This Release Note is for the SPI-4.2 (POS-PHY L4) v8.4 released in 9.2i IP Update 1, and contains the following information: 

- New Features 

- Bug Fixes 

- General Information 

- Known Issues 

 

For installation instructions and design tools requirements, see (Xilinx Answer 25222)

Patch is needed to address source core issues. See (Xilinx Answer 29705).

Solution

New Features in v8.4  

 

- Support added for ISE 9.2i. 

- Option to include IDELAYCTRL modules in design or wrapper. 

- Option to generate full rate clock (SysClk0_GP) using DCM. 

 

Bug Fixes in v8.4  

 

- CR442212: The sink core in Full_Burst read mode duplicates data in hardware when the ratio of SnkFFClk to RDClkDiv_GP is greater than or equal to 2. 

- CR438776: Sink Core: SnkBusErrStat signals are misaligned by 1 clock cycle. 

- CR438764: Sink Core: Reserve control word causes data to be dropped so that SnkPayloadErr is not asserted. 

 

General Information 

 

- Version 8.4 of the SPI-4.2 Core supports Virtex-4 and Virtex-5 family. For Virtex-II and Virtex-II Pro designs, use the latest version of the v6.x series of the SPI-4.2 Core.  

- The Version 8.4 Core is compatible with ISE 9.2i Service Pack 1. 

- If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 User Guide. 

(Xilinx Answer 29124)) Migrating SPI4.2 design from v8.3 to v8.4 

(Xilinx Answer 20430) What is the power consumption of the SPI-4.2 Core? 

(Xilinx Answer 15500) How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?  

(Xilinx Answer 20017) Which I/O Standards are supported for the SPI-4.2 Core?  

 

Known Issues in v8.4 

 

Constraints and Implementation Issues 

 

(Xilinx Answer 20000) When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear 

(Xilinx Answer 21439) When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear 

(Xilinx Answer 21320) When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear 

(Xilinx Answer 21363) PAR has problems placing components or completely routing the SPI4.2 design in my design 

(Xilinx Answer 20280) Placement failures occur in PAR when the SPI-4.2 FIFO Status Signals' I/O Standard is set to LVTTL I/O 

(Xilinx Answer 20040) Timing Analyzer (TRCE) reports "0 items analyzed".."  

(Xilinx Answer 20319) When running implementation, undefined I/O (single-ended) defaults to LVCMOS causes WARNINGS in NGDBuild 

 

General Simulation Issues 

 

(Xilinx Answer 24027) Compiling XilinxCoreLib gives error: "Error-[URMI] Instances with unresolved modules remain in the design" 

(Xilinx Answer 24026) When running simulation on SPI-4.2 design, Locked_RDClk (from RDClk DCM) might get de-asserted after PhaseAlignRequest 

(Xilinx Answer 21319) When running timing simulation on an SPI4.2 design example, several "TDat Error: Data Mismatch" messages are reported 

(Xilinx Answer 21322) When running timing simulation on a SPI4.2 design, several SETUP, HOLD, and RECOVERY violations occur 

(Xilinx Answer 20030) When simulating an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation 

(Xilinx Answer 15578) When simulating an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur 

 

SPI- 4.2 (PL4) v8.3 KNOWN ISSUES 

- The SPI-4.2 v8.3 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v8.3 issues, see (Xilinx Answer 23846)

 

SPI- 4.2 (PL4) v8.2 KNOWN ISSUES 

- The SPI-4.2 v8.2 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v8.2 issues, see (Xilinx Answer 23846)

 

SPI- 4.2 (PL4) v8.1 KNOWN ISSUES 

- The SPI-4.2 v8.1 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v8.1 issues, see (Xilinx Answer 23487)

 

SPI- 4.2 (PL4) v7.4 KNOWN ISSUES 

- The SPI-4.2 v7.4 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v7.4 issues, see (Xilinx Answer 22300)

 

SPI- 4.2 (PL4) v7.3 KNOWN ISSUES 

- The SPI-4.2 v7.3 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v7.3 issues, see (Xilinx Answer 21918)

 

SPI- 4.2 (PL4) v7.2 KNOWN ISSUES 

- The SPI-4.2 v7.2 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v7.2 issues, see (Xilinx Answer 21032).  

 

SPI- 4.2 (PL4) v7.1 KNOWN ISSUES 

- The SPI-4.2 v7.1 Core is now obsolete. Please upgrade to the latest version of the core. For information on existing SPI-4.2 v7.1 issues, see (Xilinx Answer 20274).

AR# 25457
Date Created 09/04/2007
Last Updated 05/22/2014
Status Archive
Type General Article