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AR# 25459

LogiCORE Block Memory Generator v2.5 - Release Notes and Known Issues for 9.2i IP Update 1 (9.2i_IP1)

Description

Keywords: CORE Generator, ip1_jm, mem, memory, asynch, asymmetric, nonsymmetric, non-symmetric, block RAM, RAMB, block RAM, BRAM, RAMB16, RAMB, simulation, UniSim, SimPrim, unisims, simprims, NetGen, SDF, CORE Generator


This Release Note is for the Block Memory Generator Core v2.5 released in 9.2i IP Update 1. It contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions for IP Update #1 and design tools requirements, see (Xilinx Answer 25222).

Solution

General Information
The Xilinx Block Memory Generator v2.5 LogiCORE should be used in all new Virtex-5, Virtex-4 /-4 XA, Virtex-II, Virtex-II Pro, Spartan-II/E and Spartan-3 /-3E /-3E XA /-3A /-3 XA designs wherever a block memory is required. This core supersedes the Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores, but is not a direct drop-in replacement. A Block Memory Migration Kit is available on Xilinx.com to convert Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores to the newer Block Memory Generator Core format.

See the Block Memory Core Migration Kit available at:
http://www.xilinx.com/ipcenter/blk_mem_gen/blk_mem_gen_migration_kit.htm
Also see (Xilinx Answer 24848) for known issues of the migration kit.
and (Xilinx Answer 29168) for changes made to v2.5 XCO parameters.

A new Core Generator feature is available to upgrade the Block Memory Generator from v2.4 to v2.5. This feature is part of the Core Generator and it is visible only if you open an existing Core Generator project with a previously generated Block Memory Generator v2.4 core. See the "Upgrading a Core" section of the Core Generator User Guide (Software Manuals).

(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in the Block Memory Generator.

New Features in v2.5
- Byte Write Enable support for Spartan-3A/3A DSP devices
- Separate output register controls for Port A and Port B
- New Core Generator feature: upgrades Block Memeory Generator v2.4 to v2.5 from the Core Generator Gui.
See the "Upgrading a Core" section of the Core Generator User Guide (Software Manuals).

Bug Fixes in v2.5
CR 435009: Deep Single-Port RAM or ROM configurations of the core are implemented by cascading the 32kx1 primitive (Virtex-4) or the 64kx1 primitive (Virtex-5). DRC checks fail in these implementations because the cascade in/out pins for port B are not connected

Known Issues in v2.5
(Xilinx Answer 29168) v2.5 XCO parameters have changed
(Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX"
(Xilinx Answer 23744) Invalid address input can cause the core to generate Xs on the DOUT bus
(Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate
(Xilinx Answer 24313) The core might issue unexpected outputs and simulation warning: "# ** Warning: Functional warning at simulation time ..."
(Xilinx Answer 24804) ERROR:sim:166 - An internal error has occurred. Closing core customization GUI.

Device Issues
The Virtex-4 and Virtex-5 Errata is located at:
http://www.xilinx.com/support/mysupport.htm
The Block Memory Generator Core is subject to all block RAM issues listed in the Errata.

Block Memory Generator v2.4 Known Issues
-The Block Memory Generator v2.4 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.4 issues, see (Xilinx Answer 24555).

Block Memory Generator v2.3 Known Issues
-The Block Memory Generator v2.3 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.3 issues, see (Xilinx Answer 24229).

Block Memory Generator v2.2 Known Issues
-The Block Memory Generator v2.2 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.2 issues, see (Xilinx Answer 23849).
AR# 25459
Date Created 09/04/2007
Last Updated 08/06/2007
Status Active
Type General Article