The default Aurora initialization state machine (LANE_INIT_SM) contains an asynchronous input that can cause the state machine to go into an unknown state. This Answer Record describes the fix for this issue.
In addition to this Answer Record, Virtex-4 Aurora users should also refer to (Xilinx Answer 25469).
The LANE_INIT_SM module is a one-hot state machine that controls lane initialization. This state machine is clocked by the Aurora Core's system clock called "USER_CLK". The state machine is initialized by two signals called "TXPMA_READY" and "RXPMA_READY". TXPMA_READY and RXPMA_READY are generated by the GT11_INIT module which is synchronous to a different clock called "DCLK".
This setup results in a race condition where the LANE_INIT_SM can go into a state where all one-hot state registers are '0'. The State Machine code does not check for this illegal condition and can lock up such that the core will not self-recover. To fix the issue, the asynchronous inputs (TXPMA_READY and RXPMA_READY) must be registered by USER_CLK before entering the State Machine.
A quick VHDL example:
if (USER_CLK 'event and USER_CLK = '1') then
txpma_ready_r <= TXPMA_READY;
rxpma_ready_r <= RXPMA_READY;
if ((RESET or HARD_ERROR_RESET or not txpma_ready_r or not txpma_ready_r) = '1') then
Virtex-II Pro and Virtex-5 GTP Aurora cores are not affected by this issue.
Similar cross clock domain issues might exist in the GT11_init_rx and _tx state machines generated by Aurora. These state machines are nearly identical to those generated by the RocketIO Wizard, and the same fixes will apply. There is also the potential for the state machine to be improperly optimized, thereby causing errors. Please refer to the following Answer Records for additional information:
(Xilinx Answer 25469) - Virtex-4 RocketIO Wizard v 1.4 - GT11_INIT State Machine startup failure
(Xilinx Answer 29208) - Virtex-4 Aurora Special reset consideration for Virtex-4 Aurora designs
A patched version of Aurora v2.7 can be downloaded below. This patch is called Aurora v2.7.1 and contains the fix mentioned in this Answer Record as well as the fix mentioned in (Xilinx Answer 25469).
To install this patch:
1. Make sure you have the correct ISE version. This patch is intended for ISE 9.1.03, 9.2.01, and 9.2.02.
2. Download the file here:
3. Copy the file to the "%Xilinx%" directory.
4. Unzip the file (click Yes if asked to overwrite the files).
You can verify the patch by looking at the header in the generated HDL files. The second line of the header should read:
Project: Aurora Module Generator version 2.7.1