This Answer Record contains the Release Notes for the LogiCORE Tri-Mode Ethernet MAC v3.4 Core, which was released in 9.2i IP Update 1, and includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 25222).
- Support added for ISE 9.2i.
- Virtex-4 and Virtex-5 devices: reworked the GMII and TBI input delays to improve jitter performance. Fixed-mode IODELAYs are now instantiated on both the data and clock inputs. Users should specify the values of the delays in the UCF file.
- Updated The Address Filter defaults to prevent the passing of all-zero addresses.
- Added IOSTANDARD constraint to reset in Example Design.
- When using the Example Design Local Link RX FIFO, incorrect data can be read when toggling rd_dst_rdy_n. For more information and a way to work around this issue, see (Xilinx Answer 29660).
- The example design ucf is missing a period constraint on the rx clock. For more information, see (Xilinx Answer 29935).