After adding Verilog design files to my ISE project, Project Navigator incorrectly builds my project hierarchy.
What is causing this problem, and how do I fix it?
Synthesizing the design might give an error about missing modules even though the modules exist and are in the project.
ERROR:HDLCompilers:87 - "/my_top.v" line 98 Could not find module/primitive 'sub_mod"
Project Navigator is incorrectly building projects that include Verilog metacomments that contain the word "synthesis", for example:
/* synthesis ... */
// synthesis ...
This issue was caused by the HDL parser and has been resolved in ISE 9.2i.
Xilinx recommends using Verilog-2001 syntax, which makes designs more portable and is becoming the industry standard. For more information, see (Xilinx Answer 22608).
In a few cases, the Project Navigator HDL parser cannot correctly determine the hierarchy of a design based on the order in which the files are added to the project.
One of the following might fix this issue:
- Remove the specific file that is not displayed correctly, and then re-add it to the project.
- Remove the top-level file, and then re-add it to the project.
This issue occurs when the XST Verilog Include directory is not specified and the 'include directives in the design do not explicitly call out the path to the included files.
Set the XST Verilog Include Directories property to point to the directory where the included Verilog files reside and refresh the view (F5).