In 9.1i and previous design tools releases, I was able to set the ISERDES INTERFACE_TYPE to "NETWORKING" and the BITSLIP_ENABLE to "FALSE." Now I receive a DRC error. Why?
The ISERDES must transfer high-speed data from the serial to the parallel clock rate. To satisfy timing for this transfer, CLKDIV has a small window of timing to sample the data from the serial CLK domain. This small window becomes smaller as data rate increases. Internally, timing can be managed to satisfy this small window, but the CLK and CLKDIV inputs to the ISERDES come from external clock networks in the FPGA (BUFIO/BUFR or DCM/BUFG or PLL/BUFG). These networks ideally deliver phase-aligned clocks to the ISERDES inputs, but there is a tolerance to this alignment. The sum of the uncertainty of the external clock networks and the internal timing of CLK/CLKDIV can create a situation where the CLK/CLKDIV transfer cannot meet timing over PVT. Memory interfaces operate at a low enough data rate that they can meet timing despite the external uncertainty, but networking interfaces are spaced to go much faster than memory interfaces, such that an added mechanism is needed to guarantee timing in the ISERDES.
When BITSLIP_ENABLE is set to TRUE, it enables another rank of registers in the ISERDES that is clocked by an internally timed version of CLKDIV, such that the CLK/CLKDIV transfer does not depend on the relationship of the external clock networks. This added rank of registers is also used to perform bitslip operations (hence the attribute BITSLIP_ENABLE). The internally timed CLKDIV transfer to the actual CLKDIV domain still depends on the external relationship of CLK/CLKDIV, but this domain transfer has more flexible timing because both clocks are lower speed.
If the user ties the BITSLIP port to zero, the added rank of registers does nothing more than add one CLKDIV cycle of latency to the datapath. This extra cycle of latency allows the ISERDES to meet timing at the high data rates used in networking applications.