We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2554

NC-Verilog - How do I compile Xilinx simulation libraries for NC-Verilog? (Verilog)


For NC-Verilog, you might need to compile the HDL libraries before using them for design simulations. The advantages of the compiled approach are speed of execution and economy of memory.


For the Xilinx 6.1i and 5.1i/5.2i design tools:

Use COMPXLIB to compile the libraries. For information about using COMPXLIB, please see (Xilinx Answer 15338).

In 6.1i, COMPXLIB will compile the libraries for NC-SIM on Linux and on PC.

For 5.1i, please use the Perl script at the following link when running NC-SIM on Linux or a PC:


For the Xilinx 4.1i/4.2i design tools:

Xilinx provides a utility that compiles the HDL libraries for the NC-Verilog simulator. This utility is available at "$XILINX/bin<platform>/compile_hdl.pl" (where <platform> is "hp", "sol", or "nt").

To run this, type the following at the command line:

xilperl compile_hdl.pl


Step 1:

Create a library definitions file named "cds.lib". The "cds.lib" file defines which libraries are accessible and where they are located. It also contains statements that map logical library names to their physical directory paths.

Cadence provides a utility called "nclaunch" to set up the necessary initialization files, and to compile the Verilog source libraries. "Nclaunch" is available as part of the 2.1 and later releases. Otherwise, this is a manual process.

The "cds.lib" file can be created with any text editor. The physical locations-to-logical names must also be created before proceeding to the next step. (Use the UNIX command "mkdir".)

For example:

mkdir -p <compile_dir>/simprims_ver

If you want the logical library names to be available for all designs, use INCLUDE or SOFTINCLUDE to the location of your master "cds.lib" file.

For example:

INCLUDE $CDS_INST_DIR/share/local/xilinx/cds.lib

Edit $CDS_INST_DIR/share/local/xilinx/cds.lib to include:

DEFINE simprims_ver <compile_dir>/simprims_ver

DEFINE uni3000 <compile_dir>/uni3000

DEFINE unisims_ver <compile_dir>/unisims_ver

DEFINE uni5200 <compile_dir>/uni5200

DEFINE uni9000 <compile_dir>/uni9000

DEFINE xilinxcorelib_ver <compile_dir>/xilinxcorelib_ver

Step 2:

Create a configuration variables file called "hdl.var". The "hdl.var" file defines variables that determine how the user environment is configured. The variables (LIB_MAP, VIEW_MAP, WORK) are used to specify the search order of the libraries and views when the elaborator resolves instances.

If you want the variable settings to be available for all designs, use INCLUDE or SOFTINCLUDE to the location of your master "hdl.var" file.

For example:

INCLUDE $CDS_INST_DIR/share/local/xilinx/hdl.var

Edit $CDS_INST_DIR/share/local/xilinx/hdl.var

SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var


<compile_dir>/simprims_ver => simprims_ver, \

<compile_dir>/uni3000 => uni3000, \

<compile_dir>/unisims_ver => unisims_ver, \

<compile_dir>/uni5200 => uni5200, \

<compile_dir>/uni9000 => uni9000, \

<compile_dir>/xilinxcorelib_ver => xilinxcorelib_ver)


Depending on the family that you are simulating, you must edit the "hdl.var" file to correctly list the search order of the simulation libraries.

Step 3:

Parse and analyze the Xilinx simulation libraries using NC-Verilog.


ncvlog -messages -work simprims_ver $XILINX/verilog/src/simprims/*.v


ncvlog -messages -work uni3000 $XILINX/verilog/src/uni3000/*.v

ncvlog -messages -work unisims_ver $XILINX/verilog/src/unisims/*.v

ncvlog -messages -work uni5200 $XILINX/verilog/src/uni5200/*.v

ncvlog -messages -work uni9000 $XILINX/verilog/src/uni9000/*.v


Please see (Xilinx Answer 7859) for instructions on extracting this library.

ncvlog -messages -work xilinxcorelib_ver ./XilinxCoreLib/*.v
AR# 2554
Date 07/21/2011
Status Archive
Type General Article