AR# 2574

Foundation XVHDL: How to use READBACK in a VHDL design

Description

Keywords: Foundation, VHDL, XVHDL, Metamor, Readback
Urgency: Standard

General Description:

The information in this Solution Record documents how
to add the READBACK symbol within Foundation XVHDL


*Please note that the solutions vary slightly depending on
whether the XACTStep6 or XACTStep M1 software is being used.

Solution

1

XACTStep6 - Using READBACK
---------------------------

Please note that when instantiating READBACK in VHDL, the
following line must be added to the XDM.PRO file in the project
directory:

Options XNFMERGE -d <path_to_active>\VHDL\XLNX_LIB\<FAMILY>\

where <path_to_active> is the Foundation installation
directory (C:\ACTIVE by default), and <FAMILY> is either
XC4000, XC4000E, XC5200.

library IEEE;
use IEEE.std_logic_1164.all;

entity rdbktest is
port (
clk_in: in STD_LOGIC;
trig_in: in STD_LOGIC;
data_out: out STD_LOGIC;
rip_out: out STD_LOGIC
);
end rdbktest;

architecture rdbktest_arch of rdbktest is

component readback
port (clk, trig: in std_logic; data, rip: out std_logic);
end component;

begin

U1: readback port map (clk=>clk_in, trig=>trig_in,
data=>data_out, rip=>rip_out);

end rdbktest_arch;

2

Foundation F1.x - Using READBACK
----------------------------

--Foundation F1.3/F1.4 Example of instantiating a READBACK symbol

library IEEE;
use IEEE.std_logic_1164.all;

entity rdbktest is
port (
clk_in: in STD_LOGIC;
trig_in: in STD_LOGIC;
data_out: out STD_LOGIC;
rip_out: out STD_LOGIC
);
end rdbktest;

architecture rdbktest_arch of rdbktest is

component RDCLK
port (I: in std_logic);
end component;

component RDBK
port (TRIG: in std_logic; DATA, RIP: out std_logic);
end component;

begin

U1: RDCLK port map (I=>clk_in);

U2: RDBK port map (TRIG=>trig_in, DATA=>data_out, RIP=>rip_out);

end rdbktest_arch;





AR# 2574
Date 01/02/2000
Status Archive
Type General Article