AR# 2579


8.1i CPLD XC9500 - How do I utilize the Wired-AND (WAND) in the UIM?


How do I utilize the Wired-AND capabilities in the UIM of an XC9500?

(NOTE: This capability does not exist for XC9500XL/XV devices.)


2.1i and newer versions

By default, the XC9500 fitter will attempt to automatically utilize this feature if it is needed. However, if you wish to force this utilization, you may do so by attaching the following attribute on the desired AND gate in the User Constraints File (UCF):

NET signal_name WIREAND;

where "signal_name" is the output signal of the AND gate.

NOTE: The Wired-AND feature is implemented in the UIM. Thus, the inputs to the desired AND gate must come from feedback loops. If any of the AND gate inputs are from input pins, the UIM Wired-AND cannot be used to implement the AND gate.

Additionally, a Wired-AND function may be implemented only in the UIM for a single level of logic.

For example, if your equation looks like:

Y = A*B*C

it may be implemented as a wired-AND.

However, if your function looks like:

Z = A*B + C*D

you cannot implement the function "Z" as one single wired-AND gate; you must have two AND gates to implement this. The software will typically not use Wired-AND unless a function block is running low on inputs.

Additionally, wired-AND will be used whenever an internal tristate buffer (such as BUFT) is present in the design. In this case, the wired-AND will be used and cannot be disabled by the 'Enable UIM optimization' setting in the ISE software.


Place the following attribute on the desired AND gate:


AR# 2579
Date 05/07/2014
Status Archive
Type General Article
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