AR# 2595: Foundation XVHDL, F1.3/F1.4: How to instantiate Logiblox components
AR# 2595
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Foundation XVHDL, F1.3/F1.4: How to instantiate Logiblox components
Description
Keywords: Logiblox, XVHDL, instantiate
Urgency: Standard
General Description:
How can I generate Logiblox modules and then instantiate them in a VHDL design?
Solution
1
F1.3 ==== Use the Logiblox... option in the Tools menu of the Foundation Project Manager to create the desired Logiblox component.
Then, simply instantiate the component in the VHDL code, as shown below. The file <logi_component>.VHI, located in the project directory, will provide a template for instantiating the component in the VHDL file.
The following is an example of an instantiated Logiblox 16x4 Synchronous RAM module.
library IEEE; use IEEE.std_logic_1164.all;
entity RAM_TOP is port ( a_top, di_top: in STD_LOGIC_VECTOR (3 downto 0); wr_en_top, wr_clk_top: in STD_LOGIC; do_top: out STD_LOGIC_VECTOR (3 downto 0) ); end RAM_TOP;
architecture ram_top_arch of ram_top is
component my_sram --my_sram is the name of the Logiblox component PORT(A: IN std_logic_vector(3 DOWNTO 0); DI: IN std_logic_vector(3 DOWNTO 0); WR_EN: IN std_logic; WR_CLK: IN std_logic; DO: OUT std_logic_vector(3 DOWNTO 0)); end component;
begin
U1 : my_sram port map(A=>A_TOP, DI=>DI_TOP, WR_EN=>WR_EN_TOP, WR_CLK=>WR_CLK_TOP, DO=>DO_TOP); end ram_top_arch;
2
F1.4 ==== In F1.4, you can use the Logiblox GUI via the HDL Editor, by selecting Synthesis->Logiblox.
Then, simply instantiate the component in the VHDL code, as shown below. The file <logi_component>.VHI, located in the project directory, will provide a template for instantiating the component in the VHDL file.
The following is an example of an instantiated Logiblox 16x4 Synchronous RAM module.
library IEEE; use IEEE.std_logic_1164.all;
entity RAM_TOP is port ( a_top, di_top: in STD_LOGIC_VECTOR (3 downto 0); wr_en_top, wr_clk_top: in STD_LOGIC; do_top: out STD_LOGIC_VECTOR (3 downto 0) ); end RAM_TOP;
architecture ram_top_arch of ram_top is
component my_sram --my_sram is the name of the Logiblox component PORT(A: IN std_logic_vector(3 DOWNTO 0); DI: IN std_logic_vector(3 DOWNTO 0); WR_EN: IN std_logic; WR_CLK: IN std_logic; DO: OUT std_logic_vector(3 DOWNTO 0)); end component;
begin
U1 : my_sram port map(A=>A_TOP, DI=>DI_TOP, WR_EN=>WR_EN_TOP, WR_CLK=>WR_CLK_TOP, DO=>DO_TOP); end ram_top_arch;