FPGA configuration fails with the INIT pin driving Low early. INIT goes Low in the middle of a frame, even before the first CCLK edge is sent (this is not related to a CRC error). This is a result of the activation of the Boundary Scan circuitry.
During the time that INIT is Low, the Boundary Scan (JTAG) circuitry of the XC4000 and XC5200 FPGAs is active. Activity on these pins can cause the device to enter a boundary scan active state, which interrupts the configuration.
You can use the following methods to prevent this from occurring:
1. Do not use TCK as user I/O.
2. Use TCK as output only; no other driver can toggle this pin.
3. Set TMS = High during configuration. This keeps the boundary scan state machine in the TEST-LOGIC-RESET state.