General Description: When I am compiling a VHDL or Verilog design for Synopsys, the following error occurs:
"Error: The entity 'add_sub_ub' depends on the package 'std_logic_arith' which has been analyzed more recently. Please re-analyze the source file for 'add_sub_ub' and try again. (LBR-28) Information: Compile terminated abnormally. (OPT-100)"
What does this error mean?
This error usually means that the DesignWare and Simulation Libraries are older than the current version of Synopsys, and they need to be re-compiled. For additional information on how to re-compile DesignWare and Simulation libraries, refer to (Xilinx Answer 1189).
Another possible cause of this problem is that the define_design_lib and synthetic_library variables in the ".synopsys_dc.setup" file are not consistent. For example, if the define_design_lib and synthetic_library are set:
In the first case, the define_design_lib is pointing to XC4000ex XDW, but the synthetic_library is pointing to the XC4000E .sldb file.
In the second case, the synthetic_library is okay, but the define_design_lib is pointing to the XC4000E XDW files, instead of the XC4000EX. Make sure your variables are consistent. Either use the example ".synopsys_dc.setup" files in "$XILNX/synopsys/examples," make sure XC4000E path and files are used together, or make sure XC4000EX path and files are used together.