AR# 2688: M1, ViewSynthesis: Bus Naming and Post-place-and-route Bus Reconstruction
AR# 2688
M1, ViewSynthesis: Bus Naming and Post-place-and-route Bus Reconstruction
Description
Keywords: EDIF, EDIFNETO, Viewsynthesis, bus pins, NGD2VHDL
Urgency: Standard
When an EDIF netlist is written by ViewLogic's EDIFNETO, all bussed signals and pins are expanded. The individual signal and pin names created by the expansion do not contain any special characters to delimit the bus indices. For example a bus named B[3:0] is translated into 4 signals: B3, B2, B1, B0.
NGD2VHDL can reconstruct vectors only if a delimiting character is used in the signal names. Without a delimiter the results are unpredictable. For example, a bus named CACHE2[3:0] would be flattened to CHACHE23 to CACHE20, and likely reconstructed as CACHE[23:20]. Therefore, it is not be desirable to alter NGD2VHDL to reconstruct vectors in the absence of index delimiters.
A better solution would be for ViewLogic's EDIFNETO to write bus delimiters or use port array constructs. In fact, ViewLogic is planning to support this functionality in future releases of Workview Office.
Solution
1
The post place and route timing simulation will employ different test vectors and different test criteria than functional simulation, and so the user is already burdened with writing and maintaining multiple testbenches. It is unfortunate that the user is also required to write testbenches with bussed and non-bussed entities. The following example will hopefully aid in that process.
Step 1: During initial setup of SpeedWave define the library search order in the VSSLIB.INI file. Instead of using the suggested user.lib file in the project area, define two libraries for pre- and post-place-and-route VHDL. For example, funtional.lib & timing.lib, or before.lib & after.lib. Then when analyzing the original bussed VHDL make sure that the first user library is the working library, and when analyzing the non-bussed VHDL that the second user library is the working library. When the test bench instantiates the top-level components it must differentiate between two components with the same name but with different port structure. If these top-level components are analyzed into the same library, the most recently analyzed will overwrite the entity already in the library, even if they have different architectures.
Step 2: Declare these two libraries in the test_bench.vhdl file. For example:
LIBRARY functional;
LIBRARY timing;
LIBRARY ieee;
Step 3: Include both component declarations in the architecture clause of the test bench. Instantiate, drive, and test both components.
Example: An 8-bit register is taken through this flow:
The source VHDL file, reg.vhd, is compiled through ViewSynthesis to produce wir/reg.1. After EDIFNETO, reg.edn is created and taken to the Xilinx M1 Design Manager. Take the file rev#/ver#/xc4000xe.ngd (replace #s with the current revision and version) and rename it to reg_ppr.ngd. Run NGD2VHDL to create reg_ppr.vhd.
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-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.4 -- Date: Wed Aug 06 13:25:03 1997 -- Design file: reg_ppr.ngd -- Device: xc4000ex ----- CELL ROC ----- -- Model for Reset-On-Configuration Cell
library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all;
entity ROC is generic ( InstancePath: STRING := "*"; WIDTH : Time := 0 ns) ; port( O : out std_ulogic := '1' ) ; attribute VITAL_LEVEL0 of ROC : entity is TRUE ; end ROC ;
architecture ROC_V of ROC is attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ; begin ONE_SHOT: process begin if (WIDTH <= 0 ns) then assert FALSE report "*** Error: a positive value of WIDTH must be specified ***" severity failure; else wait for WIDTH; O <= '1' ; -- altered with '1' end if; wait; end process ONE_SHOT ; end ROC_V ;
configuration CFG_ROC_V of ROC is for ROC_V end for ; end CFG_ROC_V ; ----- CELL TOC ----- -- Model for Tristate-On-Configuration Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all;
entity TOC is generic ( InstancePath: STRING := "*"); port( O : out std_ulogic := '0' ) ; attribute VITAL_LEVEL0 of TOC : entity is TRUE ; end TOC ;
architecture TOC_V of TOC is attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ; begin ONE_SHOT: process begin wait; end process ONE_SHOT ; end TOC_V ;
configuration CFG_TOC_V of TOC is for TOC_V end for ; end CFG_TOC_V ; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity REG is port ( RESET : in STD_LOGIC := 'X' ; Q7 : out STD_LOGIC ; Q6 : out STD_LOGIC ; Q5 : out STD_LOGIC ; Q4 : out STD_LOGIC ; Q3 : out STD_LOGIC ; Q2 : out STD_LOGIC ; Q1 : out STD_LOGIC ; Q0 : out STD_LOGIC ; D7 : in STD_LOGIC := 'X' ; D6 : in STD_LOGIC := 'X' ; D5 : in STD_LOGIC := 'X' ; D4 : in STD_LOGIC := 'X' ; D3 : in STD_LOGIC := 'X' ; D2 : in STD_LOGIC := 'X' ; D1 : in STD_LOGIC := 'X' ; D0 : in STD_LOGIC := 'X' ; CLK : in STD_LOGIC := 'X' ) ; end REG ;
architecture STRUCTURE of REG is component ROC port ( O : out STD_ULOGIC ) ; end component ; component TOC port ( O : out STD_ULOGIC ) ; end component ; signal FPN_CLK , FPN_D0 , FPN_D1 , FPN_D2 , FPN_D3 , FPN_D4 , FPN_D5 , FPN_D6 , FPN_D7 , FPN_Q0 , FPN_Q1 , FPN_Q2 , FPN_Q3 , FPN_Q4 , FPN_Q5 , FPN_Q6 , FPN_Q7 , FPN_RESET , GSR , VLU_Q_1_8_GSR_OR , VLU_Q_1_1_GSR_OR , VLU_Q_1_4_GSR_OR , VLU_Q_1_3_GSR_OR , VLU_Q_1_2_GSR_OR , VLU_Q_1_5_GSR_OR , VLU_Q_1_6_GSR_OR , VLU_Q_1_7_GSR_OR , Q_1I16_GTS_TRI , GTS , Q_1I26_GTS_TRI , Q_1I17_GTS_TRI , Q_1I23_GTS_TRI , Q_1I22_GTS_TRI , Q_1I32_GTS_TRI , Q_1I33_GTS_TRI , Q_1I19_GTS_TRI , Q_1I16_GTS_TRI_2_INV , Q_1I26_GTS_TRI_2_INV , Q_1I17_GTS_TRI_2_INV , Q_1I23_GTS_TRI_2_INV , Q_1I22_GTS_TRI_2_INV , Q_1I32_GTS_TRI_2_INV , Q_1I33_GTS_TRI_2_INV , Q_1I19_GTS_TRI_2_INV , GND , VDD , NGD2VHDL_X_5_0 : STD_LOGIC ; begin Q_1I7 : X_BUF port map ( I => D2 , O => FPN_D2 ) ; Q_1I33 : X_BUF port map ( I => FPN_Q6 , O => Q_1I33_GTS_TRI ) ; GND_5 : X_ZERO port map ( O => NGD2VHDL_X_5_0 ) ; VLU_Q_1_8 : X_FF port map ( I => FPN_D0 , CLK => FPN_CLK , CE => VDD , SET => GND , RST => VLU_Q_1_8_GSR_OR , O => FPN_Q0 ) ; Q_1I45 : X_CKBUF port map ( I => CLK , O => FPN_CLK ) ; Q_1I12 : X_BUF port map ( I => D3 , O => FPN_D3 ) ; Q_1I15 : X_BUF port map ( I => D4 , O => FPN_D4 ) ; Q_1I16 : X_BUF port map ( I => FPN_Q0 , O => Q_1I16_GTS_TRI ) ; Q_1I17 : X_BUF port map ( I => FPN_Q4 , O => Q_1I17_GTS_TRI ) ; Q_1I18 : X_BUF port map ( I => D5 , O => FPN_D5 ) ; Q_1I19 : X_BUF port map ( I => FPN_Q5 , O => Q_1I19_GTS_TRI ) ; Q_1I22 : X_BUF port map ( I => FPN_Q2 , O => Q_1I22_GTS_TRI ) ; Q_1I23 : X_BUF port map ( I => FPN_Q3 , O => Q_1I23_GTS_TRI ) ; Q_1I26 : X_BUF port map ( I => FPN_Q1 , O => Q_1I26_GTS_TRI ) ; VLU_Q_1_1 : X_FF port map ( I => FPN_D7 , CLK => FPN_CLK , CE => VDD , SET => GND , RST => VLU_Q_1_1_GSR_OR , O => FPN_Q7 ) ; Q_1I29 : X_BUF port map ( I => D7 , O => FPN_D7 ) ; Q_1I30 : X_BUF port map ( I => D6 , O => FPN_D6 ) ; Q_1I32 : X_BUF port map ( I => FPN_Q7 , O => Q_1I32_GTS_TRI ) ; VLU_Q_1_4 : X_FF port map ( I => FPN_D4 , CLK => FPN_CLK , CE => VDD , SET => GND , RST => VLU_Q_1_4_GSR_OR , O => FPN_Q4 ) ; Q_1I4 : X_BUF port map ( I => D0 , O => FPN_D0 ) ; Q_1I40 : X_BUF port map ( I => RESET , O => FPN_RESET ) ; VLU_Q_1_3 : X_FF port map ( I => FPN_D5 , CLK => FPN_CLK , CE => VDD , SET => GND , RST => VLU_Q_1_3_GSR_OR , O => FPN_Q5 ) ; VLU_Q_1_2 : X_FF port map ( I => FPN_D6 , CLK => FPN_CLK , CE => VDD , SET => GND , RST => VLU_Q_1_2_GSR_OR , O => FPN_Q6 ) ; VLU_Q_1_5 : X_FF port map ( I => FPN_D3 , CLK => FPN_CLK , CE => VDD , SET => GND , RST => VLU_Q_1_5_GSR_OR , O => FPN_Q3 ) ; VLU_Q_1_6 : X_FF port map ( I => FPN_D2 , CLK => FPN_CLK , CE => VDD , SET => GND , RST => VLU_Q_1_6_GSR_OR , O => FPN_Q2 ) ; VLU_Q_1_7 : X_FF port map ( I => FPN_D1 , CLK => FPN_CLK , CE => VDD , SET => GND , RST => VLU_Q_1_7_GSR_OR , O => FPN_Q1 ) ; Q_1I6 : X_BUF port map ( I => D1 , O => FPN_D1 ) ; VDD_ONE : X_ONE port map ( O => VDD ) ; VLU_Q_1_8_GSR_OR_48 : X_OR2 port map ( I0 => FPN_RESET , I1 => GSR , O => VLU_Q_1_8_GSR_OR ) ; VLU_Q_1_1_GSR_OR_49 : X_OR2 port map ( I0 => FPN_RESET , I1 => GSR , O => VLU_Q_1_1_GSR_OR ) ; VLU_Q_1_4_GSR_OR_50 : X_OR2 port map ( I0 => FPN_RESET , I1 => GSR , O => VLU_Q_1_4_GSR_OR ) ; VLU_Q_1_3_GSR_OR_51 : X_OR2 port map ( I0 => FPN_RESET , I1 => GSR , O => VLU_Q_1_3_GSR_OR ) ; VLU_Q_1_2_GSR_OR_52 : X_OR2 port map ( I0 => FPN_RESET , I1 => GSR , O => VLU_Q_1_2_GSR_OR ) ; VLU_Q_1_5_GSR_OR_53 : X_OR2 port map ( I0 => FPN_RESET , I1 => GSR , O => VLU_Q_1_5_GSR_OR ) ; VLU_Q_1_6_GSR_OR_54 : X_OR2 port map ( I0 => FPN_RESET , I1 => GSR , O => VLU_Q_1_6_GSR_OR ) ; VLU_Q_1_7_GSR_OR_55 : X_OR2 port map ( I0 => FPN_RESET , I1 => GSR , O => VLU_Q_1_7_GSR_OR ) ; Q_1I16_GTS_TRI_56 : X_TRI port map ( I => Q_1I16_GTS_TRI , O => Q0 , CTL => Q_1I16_GTS_TRI_2_INV ); Q_1I26_GTS_TRI_57 : X_TRI port map ( I => Q_1I26_GTS_TRI , O => Q1 , CTL => Q_1I26_GTS_TRI_2_INV ); Q_1I17_GTS_TRI_58 : X_TRI port map ( I => Q_1I17_GTS_TRI , O => Q4 , CTL => Q_1I17_GTS_TRI_2_INV ); Q_1I23_GTS_TRI_59 : X_TRI port map ( I => Q_1I23_GTS_TRI , O => Q3 , CTL => Q_1I23_GTS_TRI_2_INV ); Q_1I22_GTS_TRI_60 : X_TRI port map ( I => Q_1I22_GTS_TRI , O => Q2 , CTL => Q_1I22_GTS_TRI_2_INV ); Q_1I32_GTS_TRI_61 : X_TRI port map ( I => Q_1I32_GTS_TRI , O => Q7 , CTL => Q_1I32_GTS_TRI_2_INV ); Q_1I33_GTS_TRI_62 : X_TRI port map ( I => Q_1I33_GTS_TRI , O => Q6 , CTL => Q_1I33_GTS_TRI_2_INV ); Q_1I19_GTS_TRI_63 : X_TRI port map ( I => Q_1I19_GTS_TRI , O => Q5 , CTL => Q_1I19_GTS_TRI_2_INV ); Q_1I16_GTS_TRI_2_INV_64 : X_INV port map ( I => GTS , O => Q_1I16_GTS_TRI_2_INV ) ; Q_1I26_GTS_TRI_2_INV_65 : X_INV port map ( I => GTS , O => Q_1I26_GTS_TRI_2_INV ) ; Q_1I17_GTS_TRI_2_INV_66 : X_INV port map ( I => GTS , O => Q_1I17_GTS_TRI_2_INV ) ; Q_1I23_GTS_TRI_2_INV_67 : X_INV port map ( I => GTS , O => Q_1I23_GTS_TRI_2_INV ) ; Q_1I22_GTS_TRI_2_INV_68 : X_INV port map ( I => GTS , O => Q_1I22_GTS_TRI_2_INV ) ; Q_1I32_GTS_TRI_2_INV_69 : X_INV port map ( I => GTS , O => Q_1I32_GTS_TRI_2_INV ) ; Q_1I33_GTS_TRI_2_INV_70 : X_INV port map ( I => GTS , O => Q_1I33_GTS_TRI_2_INV ) ; Q_1I19_GTS_TRI_2_INV_71 : X_INV port map ( I => GTS , O => Q_1I19_GTS_TRI_2_INV ) ; GND_72 : X_ZERO port map ( O => GND ) ; ROC_NGD2VHDL : ROC port map ( O => GSR ) ; TOC_NGD2VHDL : TOC port map ( O => GTS ) ; end STRUCTURE ;
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The test bench that drives both simulations is annotated here:
-- example of test bench for 8-bit register contained in reg.vhd -- Philip Labee, Xilinx Inc., 29 July 1997 -- ------------------ test_bench.vhd
LIBRARY functional; LIBRARY timing; LIBRARY ieee; LIBRARY synth; USE ieee.std_logic_1164.ALL; USE synth.vhdlsynth.all;
ENTITY reg_test IS END reg_test; -----
ARCHITECTURE test OF reg_test IS
component REG_BEFORE port( reset: IN std_logic; clk : IN std_logic; d : IN std_logic_vector(7 DOWNTO 0); q : OUT std_logic_vector(7 DOWNTO 0)); end component;
component REG_AFTER port( RESET : in STD_LOGIC ; Q7 : out STD_LOGIC ; Q6 : out STD_LOGIC ; Q5 : out STD_LOGIC ; Q4 : out STD_LOGIC ; Q3 : out STD_LOGIC ; Q2 : out STD_LOGIC ; Q1 : out STD_LOGIC ; Q0 : out STD_LOGIC ; D7 : in STD_LOGIC ; D6 : in STD_LOGIC ; D5 : in STD_LOGIC ; D4 : in STD_LOGIC ; D3 : in STD_LOGIC ; D2 : in STD_LOGIC ; D1 : in STD_LOGIC ; D0 : in STD_LOGIC ; CLK : in STD_LOGIC ); end component;
for func_sim : REG_BEFORE use entity FUNCTIONAL.reg(behav); for ppr_func : REG_AFTER use entity TIMING.reg(structure);
signal byte_IN, byte_OUT : std_logic_vector(7 DOWNTO 0); signal bin_7, bin_6, bin_5, bin_4, bin_3, bin_2, bin_1, bin_0 : std_logic; signal bot_7, bot_6, bot_5, bot_4, bot_3, bot_2, bot_1, bot_0 : std_logic; signal rst, clock : std_logic; signal start_stop : std_logic;
IF (start_stop='0' AND start_stop'EVENT) THEN assert (bin_7=bot_7 AND bin_6=bot_6 AND bin_5=bot_5 AND bin_4=bot_4 AND bin_3=bot_3 AND bin_2=bot_2 AND bin_1=bot_1 AND bin_0=bot_0) report "post place and route FUNCTIONAL mismatch" severity warning;
assert false report "done" severity warning; END IF; END process stimulus_T;
END test;
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-- example of 8-bit register which is instantiated in test_bench.vhd -- Philip Labee, Xilinx Inc., 29 July 1997 -- ------------------ REG.VHD
LIBRARY ieee; LIBRARY synth; USE ieee.std_logic_1164.ALL; USE synth.vhdlsynth.all;
ENTITY reg IS PORT ( reset, clk : IN std_logic; d : IN std_logic_vector(7 DOWNTO 0) ; q : OUT std_logic_vector(7 DOWNTO 0)); END reg; ----- ARCHITECTURE behav OF reg IS BEGIN PROCESS(clk, reset) BEGIN IF (reset='1') THEN q<= "00000000"; ELSIF(clk='1' AND clk'EVENT) THEN q <= d; END IF; END PROCESS; END behav;