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AR# 2719

CPLD - How do I lock the pins/control placement?


General Description:

How do I control the pin-out of a design with pin assignments?


Pin-out controlled by Pin Locking:

If you have successfully fit a design into a CPLD device, and you build a prototype containing the device, you will probably want to "lock" the pin-out.

In Foundation ISE, go to the Processes tab; under "Implement Design" is the option to "Lock Pins." Double-clicking on this will write the current pin-out to the yourproject.ucf file.

Pin-out controlled by Pin and Function Block Assignment:

A. Pin Assignment

Use the UCF file to specify your LOC constraint. The proper syntax is:


For pinned-type packages, the pin_name takes the form "Pnn" where "nn" is a number. For example, for the PC84 package, the valid range for pin_name is P1 through P84. For grid array-type packages (FG and BG), the pin_name takes the form "rc", where "r" is the row letter and "c" is the column number.

B. Function Block/Macrocell Assignment

You may explicitly assign internal nodes in your design to specific function blocks or even specific macrocells of the target device. To assign an internal node to a specific location, apply the following attribute to a symbol or its output net:


where "nn" is a valid function block number and "mm" (optional) is a valid macrocell number for the target device.

The correct UCF file syntax is:

INST COMPONENTNAME LOC=FBnn[_mm]; # For a symbol

For example:

INST MY_FLOP LOC=FB1_3; # This would lock register MY_FLOP to Function block 1, Macrocell 3.


NET NETNAME LOC=FBnn[_mm]; # For a net

For example:

NET MY_FLOP_OUT LOC=FB2_4; # This would lock the node/net MY_FLOP_OUT to Function block 2, Macrocell 4.

Pin Assignment Precautions:

You may apply the LOC attribute to as many signals in your design as you wish. However, each pin assignment further constrains the software, making it more difficult for the fitter to automatically allocate logic and I/O resources for the remaining I/O signals in your design.

When you manually assign output and I/O pins, the software is forced to place associated logic functions into specific macrocells and specific function blocks. If the associated logic does not exceed the available function block resources (macrocells, product terms, and function block inputs), the logic is mapped into the macrocell.

It is usually best to allow the fitter to automatically assign most or all of the pins based on the most efficient placement of logic in the device. The fitter automatically establishes a pin-out that best allows for future design iterations without pin relocation. Any manual pin assignments made in your design may not allow as much tolerance for changes in the logic associated with those pins and in the logic physically mapped to nearby locations in the device.

If you are assigning pin locations to signals used as clocks, asynchronous set/reset, or output enable in your design, assign them to the GCK, GSR and GTS pins on the device if you wish to take advantage of these global resources. The fitter will still automatically assign other clock, set/reset and output enable inputs to any available GCK, GSR and GTS pins that remain.

Ignoring the LOC Attribute

If your schematic contains LOC attributes, or if you are using a UCF file to specify pin locations and you wish to let the fitter automatically assign all I/O pins, you can set the fitter to ignore all LOC attributes. This allows you to temporarily ignore all the LOC attributes in your schematic and/or UCF file.

This is useful if you want to test the way your design fits a different target device without removing all the LOC attributes from your schematic. This option is located in the Implementation Options and is named "Use Design Location Constraints."

AR# 2719
Date 02/03/2013
Status Active
Type General Article