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AR# 2805

Synplify - How do I instantiate Boundary Scan (BSCAN) in HDL (Verilog/VHDL)?

Description


General Description:

How do I instantiate BSCAN in HDL for Synplify?

Solution


<b.XC4000e/ex/xl, Spartan/XL - Boundary SCAN Verilog Code



`include "<install_area>/synplcty/lib/xilinx/xc4000.v"



module bnd_scan (D_IN, CLK, Q_OUT);

input D_IN, CLK;

output Q_OUT;

reg Q_OUT;



wire TCK_P, TDI_P, TMS_P, TDO_P;



BSCAN U1 (.TDO (TDO_P), .TDI (TDI_P), .TMS (TMS_P), .TCK (TCK_P);



TDI U2 (.I (TDI_P));



TCK U3 (.I (TCK_P));



TMS U4 (.I (TMS_P));



TDO U5 (.O (TDO_P));



// User logic here

always @(posedge CLK)

Q_OUT <= D_IN;



endmodule



XC4000e/ex/xl, Spartan/XL - Boundary SCAN VHDL Code



library IEEE;

use IEEE.std_logic_1164.all;

library xc4000;

use xc4000.components.all;



entity bnd_scan is

port (D_IN, CLK: in bit;

Q_OUT: out bit);

end bnd_scan;



architecture xilinx of bnd_scan is



signal TCK_P, TDI_P, TMS_P, TDO_P : STD_LOGIC;



begin



U0: BSCAN port map (TDO => TDO_P, TDI => TDI_P,

TMS => TMS_P, TCK => TCK_P;



U1: TDI port map (I => TDI_P);



U2: TCK port map (I => TCK_P);



U3: TMS port map (I => TMS_P);



U4: TDO port map (O => TDO_P);



-- User logic here

process (CLK)

begin

if posedge(CLK) then

Q_OUT <= D_IN;

end if;

end process;



end xilinx;



The BSCAN component indicates that boundary scan logic should be enabled after the programmable logic device (PLD) configuration is complete. It also provides optional access to some special features of the XC5200 boundary scan logic. To indicate that BSCAN should remain enabled after configuration, connect the BSCAN component to the TDI, TMS, TCK, and TDO pins.



For Virtex and Spartan-II, the JTAG ports are dedicated and always available. The BSCAN symbol is not needed for basic JTAG functions, or for multiple Boundary Scan operations.



For advanced JTAG users, BSCAN_VIRTEX/BSCAN_SPARTAN2 is available to access and control the user registers created with Boundary Scan TAP controller.



You can instantiate a BSCAN cell by using the Xilinx family library supplied with Synplify. Please see (Xilinx Solution 244) for details on instantiating Xilinx-specific cells.



NOTE: Please see (Xilinx Solution 4641) for information on how to instantiate the JTAG pins for general I/O in HDL.

-----------------------------------------------------------------------

XC5200 - Boundary SCAN Verilog Code



module bnd_scan (D_IN, CLK, Q_OUT);

input D_IN, CLK;

output Q_OUT;

reg Q_OUT;



wire TCK_P, TDI_P, TMS_P, TDO_P;



BSCAN U0 (.TDO (TDO_P), .TDI (TDI_P), .TMS (TMS_P), .TCK (TCK_P));



TDI U1 (.I (TDI_P));



TCK U2 (.I (TCK_P));



TMS U3 (.I (TMS_P));



TDO U4 (.O (TDO_P));



// User logic here

always @(posedge CLK)

Q_OUT <= D_IN;



endmodule



module TDI(I) /* synthesis black_box */;

output I /* synthesis .ispad=1 */;

endmodule



module TCK(I) /*synthesis black_box*/;

output I /*synthesis .ispad=1*/;

endmodule



module TMS(I) /*synthesis black_box*/;

output I /*synthesis .ispad=1*/;

endmodule



module TDO(O) /*synthesis black_box .noprune=1 */;

input O /*synthesis .ispad=1*/;

endmodule



module BSCAN(TDO, TCK, TDI, TMS) /* synthesis black_box */;

output TDO;

input TCK, TDI, TMS;

endmodule



XC5200 - Boundary Scan VHDL Code



library IEEE, synplify;

use IEEE.std_logic_1164.all;

use synplify.attributes.all;



entity bnd_scan is

port (D_IN, CLK : in std_logic;

Q_OUT : out std_logic);

end bnd_scan;



architecture xilinx of bnd_scan is



component BSCAN

port (TDI, TMS, TCK, TDO1, TD : in STD_LOGIC;

TDO : out STD_LOGIC);

end component;

attribute black_box of BSCAN : component is true;



component TDI

port (I : out STD_LOGIC);

end component;

attribute black_box_pad_pin of TDI : component is "I";



component TCK

port (I : out STD_LOGIC);

end component;

attribute black_box_pad_pin of TCK : component is "I";



component TMS

port (I : out STD_LOGIC);

end component;

attribute black_box_pad_pin of TMS : component is "I";



component TDO

port (O : in STD_LOGIC);

end component;

attribute black_box_pad_pin of TDO : component is "O";

attribute synthesis_noprune of TDO : component is true;



signal TCK_P, TDI_P, TMS_P, TDO_P : STD_LOGIC;



begin



U0: BSCAN port map (TDO => TDO_P, TDI => TDI_P,

TMS => TMS_P, TCK => TCK_P);



U1: TDI port map (I =>TDI_P);



U2: TCK port map (I =>TCK_P);



U3: TMS port map (I =>TMS_P);



U4: TDO port map (O =>TDO_P);



process (CLK)

begin

if posedge(CLK) then

Q_OUT<= D_IN;

end if;

end process;



end xilinx;



Virtex and Spartan-II Boundary Scan Code

NOTE: Basic boundary scan operations are always available in these devices.

BSCAN_VIRTEX/BSCAN_SPARTAN2 is connected to internal logic only.



library IEEE;

use IEEE.std_logic_1164.all;



entity flops is port(

di: in std_logic;

ce : in std_logic;

clk: in std_logic;

qo: out std_logic

);



end flops;



architecture inst of flops is

component FDCE port( D: in std_logic;

CE: in std_logic;

C: in std_logic;

CLR: in std_logic;

Q: out std_logic);

end component;



component BSCAN_VIRTEX port ( TDO1 : in std_logic;

TDO2: in std_logic;

UPDATE : out std_logic;

SHIFT: out std_logic;

RESET: out std_logic;

TDI: out std_logic;

SEL1: out std_logic;

DRCK1: out std_logic;

SEL2: out std_logic;

DRCK2: out std_logic);

end component;



signal q1,rst,tdo1,update, shift, reset, tdi,sel1,drck1 : std_logic;





begin

U4: BSCAN_VIRTEX port map(TDO1 => tdo1,

TDO2 => '0' ,

UPDATE => update,

SHIFT => shift,

RESET => rst,

TDI => tdi,

SEL1 => sel1,

DRCK1 => drck1,

SEL2 => open,

DRCK2 => open);



U0 : FDCE port map(D => di,

CE=> update,

C => clk,

CLR => shift,

Q => tdo1);



U1: FDCE port map(D => tdi,

CE=> sel1,

C => drck1,

CLR => rst,

Q => q1);



U2: FDCE port map(D => q1,

CE=> ce,

C => clk,

CLR => rst,

Q => qo);



end inst;



Virtex and Spartan-II Boundary Scan Code

NOTE: Basic boundary scan operations are always available in these devices.

BSCAN_VIRTEX/BSCAN_SPARTAN2 is connected to internal logic only.

Undriven input pins (TDO1 in this example) will be connected to GND.



module vbscan (di,clk, qo, rst);

input di;

input clk;

output qo;

input rst;



wire q0,update,shift,reset,tdi,sel1,drck1,sel2,drck2,tdo1,tdo2;



BSCAN_VIRTEX bscanvirtex(.TDO1(), .TDO2(tdo2),

.UPDATE(update),.SHIFT(shift),

.RESET(reset),

.TDI(tdi),

.SEL1(),

.DRCK1(),

.SEL2(sel2),

.DRCK2(drck2)) ;



FDCE u0(.D(di),

.CE(update),

.C (clk),

.CLR (reset),

.Q (tdo2));



FDCE u1 (.D (shift),

.CE(tdi),

.C (clk),

.CLR(sel2),

.Q (q1));



FDCE u2(.D (q1),

.CE(drck2),

.C (clk),

.CLR (rst),

.Q (qo)) ;



endmodule
AR# 2805
Date Created 08/31/2007
Last Updated 04/21/2011
Status Archive
Type General Article