UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29112

9.1i Constraints - How do I create register (flip-flop) initialization values in Verilog HDL?

Description

How to initial register (flip-flop) values in Verilog?

Solution

Solution 1:

Use the 'initial' module to control the initial value of the registers during device power-up.

You can use an 'initial' module directly in Verilog source code. The module can be synthesized by XST and implemented. This solution is especially used when there is no reset logic.

Use the following for coding the initial module for inferred and instantiated logic.

For XST Synthesis

"Test" is the top-level file:

module test (clk, ina, inb, outa, outb);

input clk, ina, inb;

output outa, outb;

reg outa;

reg outb;

reg[2:0] counter;

initial

begin

counter<=0; // register counter will have a initial value of 0;

outa<=0; // register outa will have a initial value of 0;

outb<=1; // register outb will have a initial value of 1;

end

always @ (posedge clk)

begin

if(ina)

begin

counter<=counter+1;

end

else if(inb)

begin

counter<=counter-1;

end

end

always @ (posedge clk)

begin

if(counter==7)

begin

outa<=1;

outb<=0;

end

else

begin

outa<=0;

outb<=1;

end

end

endmodule

Solution 2:

Another way to work around this issue is to use the INIT attribute to control the initial value of the registers during device power-up. Use the "S" value to set on power-up, and the "R" value to reset on power-up. (The default is "reset".)

For more information, please see (Xilinx Answer 12293).

AR# 29112
Date Created 03/06/2008
Last Updated 12/15/2012
Status Active
Type General Article